DC offset correction scheme for wireless receivers

• US 20020151289A1
• Filed: 03/05/2001
• Published: 10/17/2002
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rahman, Mahibur, Schweickert, Robert, Mittel, James, Thomas, Christopher T., Powell, Clinton C. II
• Granted Patent: US 6,560,447 B2
• Time in Patent Office: Days
• US Class Current: 455/232.1
• CPC Class Codes: H03D 3/006 by sampling the oscillations and further processing the samples, e.g. by computing techniques H03D3/007 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.

Claims

1. A receiver for receiving and processing a radio frequency signal using a DC offset correction scheme within a radio communication system, the receiver comprising:

a receiver antenna for receiving the radio frequency signal;

a radio frequency frontend coupled to the receiver antenna, the radio frequency frontend comprising;

a receiver radio frequency amplifier for selecting a desired portion within a band of frequencies of the radio frequency signal, and for amplifying the desired portion, thereby generating a desired signal,

a receiver local oscillator for generating a local oscillator signal,

a receiver radio frequency mixer coupled to the output of the RF amplifier and coupled to the output of the local oscillator for converting the desired signal to a baseband signal using the local oscillator signal, and

a receiver intermediate frequency amplifier coupled to the output of the radio frequency mixer for providing a programmable intermediate frequency gain to amplify the baseband signal, thereby generating an intermediate frequency amplifier output; and

a baseband backend coupled to the radio frequency frontend, the baseband backend comprising;

an anti-aliasing filter for receiving the intermediate frequency amplifier output and for attenuating a plurality of frequency bands, thereby generating an anti-aliasing filter output,

an analog to digital converter coupled to the output of the anti-aliasing filter for converting the anti-aliasing filter output from an analog format to a digital format, thereby generating a digital signal,

a DC offset correction circuit coupled to the output of the analog to digital converter for receiving the digital signal and for calculating the average DC offset and correcting it, thereby generating a first offset correction signal and a second offset correction signal, and

a digital to analog converter coupled to the output of the DC offset correction circuit for conversion of the offset correction signal to analog form, thereby generating an analog signal, wherein the analog signal is used to DC bias the output of the receiver intermediate frequency amplifier.

2. The receiver as recited in claim 1 wherein the DC offset correction circuit comprises:

a feedback loop for shifting the digital signal by a programmable amount; and

a coarse DC offset correction path coupled to the feedback loop for performing coarse DC offset correction.

3. The receiver as recited in claim 2 wherein the feedback loop comprises:

a shifter for shifting the digital signal by the programmable amount, thereby generating a shifted signal;

a rounder coupled to the shifter for performing rounding on the shifted signal, thereby generating a rounded signal;

an integrator coupled to the rounder for averaging the rounded signal, thereby generating an average DC offset; and

a first subtractor coupled to the integrator for subtracting the average DC offset from the digital signal.

4. The receiver as recited in claim 2 wherein the coarse DC offset correction path comprises:

a round and clip circuit for rounding and clipping the average DC offset, thereby generating a rounded and clipped signal;

a second subtractor coupled to the round and clip circuit for subtracting the rounded and clipped signal from a previous coarse DC offset correction signal, thereby generating a new DC bias; and

a multiplexer coupled to the second subtractor for multiplexing the new DC bias.

5. The receiver as recited in claim 4, wherein the coarse DC offset correction path further comprises:

a DC adjustment circuit coupled to the second subtractor, wherein the DC adjustment circuit makes a very small DC adjustment to the new DC bias and then inputs the adjusted signal to the multiplexer.

6. A DC offset correction circuit for providing DC offset correction within a receiver for receiving and processing a radio frequency signal within a radio communication system, the DC offset correction circuit comprising:

a feedback loop for shifting the digital signal by a programmable amount; and

a coarse DC offset correction path coupled to the feedback loop for performing coarse DC offset correction.

7. The DC offset correction circuit as recited in claim 6, wherein the feedback loop comprises:

a shifter for shifting the digital signal by the programmable amount, thereby generating a shifted signal;

a rounder coupled to the shifter for performing rounding on the shifted signal, thereby generating a rounded signal;

an integrator coupled to the rounder for averaging the rounded signal, thereby generating an average DC offset; and

a first subtractor coupled to the integrator for subtracting the average DC offset from the digital signal.

8. The DC offset correction circuit as recited in claim 6, wherein the coarse DC offset correction path comprises:

a round and clip circuit for rounding and clipping the average DC offset, thereby generating a rounded and clipped signal;

a second subtractor coupled to the round and clip circuit for subtracting the rounded and clipped signal from a previous coarse DC offset correction signal, thereby generating a new DC bias; and

a multiplexer coupled to the second subtractor for multiplexing the new DC bias.

9. The DC offset correction circuit as recited in claim 8, wherein the coarse DC offset correction path further comprises:

a DC adjustment circuit coupled to the second subtractor, wherein the DC adjustment circuit makes a very small DC adjustment to the new DC bias and then inputs the adjusted signal to the multiplexer.