Inter-chip communication system

• US 20020152060A1
• Filed: 07/06/2001
• Published: 10/17/2002
• Est. Priority Date: 08/31/1998
• Status: Abandoned Application

• Current Assignee: Verisity Design, Inc. (Cadence Design Systems)
• Original Assignee: Verisity Design, Inc. (Cadence Design Systems)
• Inventors: Tseng, Ping-Sheng
• Application Number:
  US09/900,124
• Publication Number:
  US 20020152060A1
• Time in Patent Office: Days
• US Class Current: 703/17
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The complexity of user designs, the limited capacity of FPGA chips, and the limited number of chip pinouts have resulted in the development of inter-chip communication technology that necessitates the transfer of a large amount of data across a limited number of pins in the shortest amount of time. The inter-chip communication system transfers signals across FPGA chip boundaries only when these signals change values. Thus, no cycles are wasted and every event signal has a fair chance of achieving communication across chip boundaries. The inter-chip communication system includes a series of event detectors that detect changes in signal values and packet schedulers which can then schedule the transfer of these changed signal values to another designated chip. Working with a plurality of signal groups that represents signals at the separated connections, the event detector detects events (or changes in signal values). When an event has been detected, the event detector alerts the packet scheduler. The packet scheduler employs a token ring scheme as follows. When the packet scheduler receives a token and detects an event, the packet scheduler “grabs” the token and schedules the transmission of this packet in the next packet cycle. If, however, the packet scheduler receives the token but does not detect an event, it will pass the token to the next packet scheduler. At the end of each packet cycle, the packet scheduler that grabbed the token will pass the token to the next logic associated with another packet.

Claims

1. An inter-chip communication system for the communication of a plurality of N-bit signal groups between a first logic device and a second logic device that are coupled together through an M-bit wide conductive element, comprising:

transmission logic in the first logic device for transmitting any N-bit signal group that changed in value M bits at a time across the M-bit conductive element; and

reception logic in the second logic device for receiving the N-bit signal group.

2. The inter-chip communication system of claim 1, wherein the transmission logic further comprises:

an event detector for detecting a change in value among the N-bit signal groups and providing an event indication identifying the particular signal group that changed in value.

3. The inter-chip communication system of claim 1, wherein the transmission logic further comprises:

an event detector for each N-bit signal group for detecting a change in value in its associated N-bit signal group and providing an event indication identifying that its N-bit signal group changed in value.

4. The inter-chip communication system of claim 2, wherein N>

M and the transmission logic further comprises;

a packet scheduler for receiving the event indication and dividing the N-bit signal group associated with the event indication into M-bit data groups.

5. The inter-chip communication system of claim 3, wherein N>

M and the transmission logic further comprises;

a packet scheduler for each N-bit signal group for receiving the event indication from the event detector associated with its N-bit signal group and dividing the N-bit signal group into M-bit data groups.

6. The inter-chip communication system of claim 4, wherein the transmission logic further comprises:

scan-out logic for selecting the M-bit data groups for transmission across the M-bit conductive element.

7. The inter-chip communication system of claim 5, wherein the transmission logic further comprises:

scan-out logic for selecting the M-bit data groups for transmission across the M-bit conductive element.

8. The inter-chip communication system of claim 1, wherein each N-bit signal group is associated with an identifying header, the reception logic further comprising:

header decode unit for receiving the M-bit data groups and determining which N-bit signal group these M-bit data groups belong.

9. The inter-chip communication system of claim 5, wherein the packet scheduler is capable of receiving, holding, and passing a token.

10. The inter-chip communication system of claim 5, wherein the packet scheduler transmits its M-bit data groups when it holds a token.

11. The inter-chip communication system of claim 10, wherein the packet scheduler holds a token, when it receives the token and an event indication.

12. The inter-chip communication system of claim 10, wherein the packet scheduler passes a token, when it receives the token and no event indication has been received.

14. The data transmission communication system of claim 13, wherein N>

M the scheduler divides the N-bit signal group into a plurality of M-bit groups.

15. The data transmission communication system of claim 13, wherein the event detector network includes a plurality of event detectors and each event detector is associated with its own N-bit signal group.

16. The data transmission communication system of claim 15, wherein the event detector for each N-bit signal group detects a change in value in its associated N-bit signal group and provides an event indication identifying that its N-bit signal group changed in value.

17. The data transmission communication system of claim 15, wherein the scheduler includes a plurality of packet schedulers and each packet scheduler is associated with its own N-bit signal group.

18. The data transmission communication system of claim 16, wherein the scheduler includes a plurality of packet schedulers and each packet scheduler is associated with its own N-bit signal group.

19. The data transmission communication system of claim 18, wherein the plurality of packet schedulers decides among themselves which N-bit signal group to transmit.

20. The data transmission communication system of claim 19, wherein N>

M and each packet scheduler receives the event indication and divides the N-bit signal group associated with the event indication into M-bit data groups.

21. The data transmission communication system of claim 19, wherein the plurality of packet schedulers passes tokens to each other and depending on which packet scheduler receives an event indication, each packet scheduler holds the token or passes the token.

22. The data transmission communication system of claim 19, wherein the packet scheduler transmits its M-bit data groups when it holds a token.

23. The data transmission communication system of claim 20, wherein the packet scheduler transmits its M-bit data groups when it holds a token.

24. The data transmission communication system of claim 19, wherein the packet scheduler holds a token when it receives the token and an event indication.

25. The data transmission communication system of claim 19, wherein the packet scheduler passes a token, when it receives the token and no event indication has been received.

27. The method of claim 26, wherein N>

M and the step of processing further comprises;

dividing the N-bit signal groups into M-bit data groups, wherein the transmission data group comprises the M-bit data groups.

28. The method of claim 26, wherein the step of selecting further comprises:

identifying the N-bit signal group that experienced the change in value; and

determining when the N-bit signal group should be transmitted.

29. The method of claim 27, wherein the step of transmitting includes:

transmitting the transmission data group by transmitting, M bits at a time, each M-bit data group.

30. The method of claim 28, wherein the step of determining includes:

determining whether the identified N-bit signal group currently has a token; and

scheduling the transmission of the identified N-bit signal group if it has the token.

13. A data transmission communication system for the transmission of a plurality of N-bit signal groups from a first logic device to a second logic device that are coupled together through an M-bit wide conductive element, comprising:

an event detector network for detecting a change in value among the N-bit signal groups and providing an event indication identifying the particular signal group that changed in value; and

a scheduler for selecting the N-bit signal group that changed in value and scheduling its transmission.

26. A method of scheduling the transmission of a packet from a first logic device to a second logic device across an M-bit wide connection, the packet selected from a plurality of N-bit signal groups, comprising steps:

detecting a change in value among the N-bit signal groups;

selecting the changed N-bit signal group for transmission;

processing the N-bit signal group into a transmission data group; and

transmitting the transmission data group across the M-bit wide connection.