High-speed information retrieval system
First Claim
1. An information retrieval system for selecting a piece of information relating to a retrieval key code dividable into plural retrieval sub-codes, comprising:
- a first memory including plural memory spaces respectively storing plural groups of content codes equal in bit width to said plural retrieval sub-codes, and responsive to said plural retrieval sub-codes so as to output plural address codes representative of memory locations respectively selected from said plural memory spaces, content codes identical with said plural retrieval sub-codes being stored in said memory locations;
a second memory having plural addressable memory locations for storing pieces of information, and responsive to a target address so as to select said piece of information relating to said retrieval key code from said pieces of information; and
an address generating unit connected to said first memory and said second memory, and generating said target address through an arithmetic operation on said address codes so as to supply said target address to said second memory.
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Accused Products
Abstract
An information retrieval system includes two content addressable memories to be searched for m-bit/n-bit codes identical with m-bit/n-bit retrieval key sub-codes, a data memory storing pieces of information relating to different retrieval keys expressed by the combinations of the m-bit/n-bit codes in addressable memory locations assigned addresses, respectively, and an address generating unit supplied with addresses of the m-bit/n-bit codes identical with the m-bit/n-bit retrieval key sub-codes from the content addressable memories so as to generate a target address from the addresses for accessing the piece of information relating to a given retrieval key, whereby the two content addressable memories are searched for the m-bit/n-bit codes substantially in parallel.
26 Citations
17 Claims
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1. An information retrieval system for selecting a piece of information relating to a retrieval key code dividable into plural retrieval sub-codes, comprising:
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a first memory including plural memory spaces respectively storing plural groups of content codes equal in bit width to said plural retrieval sub-codes, and responsive to said plural retrieval sub-codes so as to output plural address codes representative of memory locations respectively selected from said plural memory spaces, content codes identical with said plural retrieval sub-codes being stored in said memory locations;
a second memory having plural addressable memory locations for storing pieces of information, and responsive to a target address so as to select said piece of information relating to said retrieval key code from said pieces of information; and
an address generating unit connected to said first memory and said second memory, and generating said target address through an arithmetic operation on said address codes so as to supply said target address to said second memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification