Memory control apparatus and method for storing data in a selected cache memory based on whether a group or slot number is odd or even

• US 20020152357A1
• Filed: 06/06/2002
• Published: 10/17/2002
• Est. Priority Date: 02/20/1995
• Status: Active Grant

• Current Assignee: Akira Yamamoto, Misako Takahashi, Shigeru Kishiro, Yoshihiro Asaka
• Original Assignee: Akira Yamamoto, Misako Takahashi, Shigeru Kishiro, Yoshihiro Asaka
• Inventors: Yamamoto, Akira, Asaka, Yoshihiro, Kishiro, Shigeru, Takahashi, Misako
• Granted Patent: US 6,611,899 B2
• Time in Patent Office: Days
• US Class Current: 711/119
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

A memory control apparatus according to the invention is interposed between a central processing unit and a memory device to store data and has: a channel control unit to control a data transfer to/from the central processing unit; a drive control unit to control a data transfer to/from the memory device; a plurality of cache memories to temporarily store the data which is transferred between the central processing unit and the memory device; and a cache memory control unit having selecting means for selecting the cache memory to store the data which is transferred from the memory device. The memory control apparatus selects the cache memory to store the data so as to almost equalize use amounts in the plurality of cache memories, thereby controlling the allocation of the cache memories and enabling a cache memory space to be effectively used.

Claims

1. A memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a plurality of cache memories for temporarily storing data of said memory device, and for transferring data between said central processing unit and said memory device, said memory control apparatus comprising:

a control unit for controlling said cache memories for assigning a cache memory for storing clean data and dirty data which is updated data corresponding the clean data and cache memory for storing said dirty data among said plurality of cache memories,

wherein said control unit assigns the cache memory in accordance with at least one of data identifier, data slot number, or a usable memory amount in cache memory.

2. A memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a plurality of cache memories for temporarily storing data of said memory device, for transferring data between said central processing unit and said memory device, said memory control apparatus comprising:

a control unit for controlling said cache memories for assigning a cache memory for storing clean data and a cache memory for storing dirty data which is updated data corresponding the clean data among said plurality of cache memories;

means for storing cache using state information of each of said plurality of cache memories,

wherein a cache memory for storing is assigned in accordance with a comparison between said cache using state information of each of said plurality of cache memories, when said control unit assigns a cache memory for storing said clean data and dirty data which is updated data concerned with said clean data, and a cache memory for storing said dirty data.

3. A memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a plurality of cache memories for temporarily storing data of said memory device, and for transferring data between said central processing unit and said memory device, wherein each of said plurality of cache memories includes at least one cache memory unit, said memory control apparatus comprising:

means for storing usable/unusable information for each cache memory unit; and

a control unit for controlling said plurality of cache memories for assigning a cache memory for storing clean data and dirty data which is updated data concerned with said clean data and a cache memory for storing said dirty data in accordance with said usable/unusable information.

4. In a memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a plurality of cache memories for temporarily storing data of said memory device, for transferring data between said central processing unit and said memory device, a cache control method, responsive to a data write request from said central processing unit, comprising the steps of:

judging whether said write request is write hit, and when said write request is a write hit, storing dirty data which is updated data concerned with clean data into a cache memory in which said clean data is stored and into a cache memory, other than said cache memory in which said clean data is stored;

when said write request is not a write hit, reading cache using state information from means for storing cache using state information indicating using state for each of said plurality of cache memories, and comparing said cache using state information of each of said plurality of cache memories; and

in response to said reading and comparing step, assigning a cache memory for writing said clean data and said dirty data and a cache memory for writing said dirty data.

5. In a memory control apparatus, which is interposed between a central processing unit and a memory device for storing data, having a plurality of cache memories for temporarily storing data of said memory device, for transferring data between said central processing unit and said memory device, a cache control method, responsive to a data write request from said central processing unit, comprising the steps of:

determining whether said write request is write hit or not, and when said write request in a write hit, storing dirty data which is updated data concerned with clean data into a cache memory in which clean data is stored and into a cache memory, other than said cache memory, in which said clean data is stored; and

when said write request is not a write hit, assigning a cache memory for writing said clean data and said dirty data and a cache memory for writing said dirty data in accordance with either one of a slot number to which a updating object number is stored or an identifier of data.