Electrostatic discharge protection structures having high holding current for latch-up immunity

• US 20020153571A1
• Filed: 03/15/2002
• Published: 10/24/2002
• Est. Priority Date: 03/16/2001
• Status: Active Grant

• Current Assignee: Sofics BVBA
• Original Assignee: Sarnoff Corporation (SRI International, Inc.)
• Inventors: Russ, Cornelius Christian, Mergens, Markus Paul Josef, Armer, John, Jozwiak, Phillip Czeslaw, Verhaege, Koen Gerard Maria
• Granted Patent: US 6,803,633 B2
• Time in Patent Office: Days
• US Class Current: 257/358
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

Abstract

An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

Claims

1. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

a silicon controlled rectifier (SCR), for coupling between a supply line of the IC and a ground line;

a first trigger device for coupling from the supply line to a first gate of the SCR;

a first substrate resistor for coupling between the first gate and the ground line; and

a first shunt resistor for coupling between the first gate and the ground line, wherein said shunt resistor has a resistance value lower than the substrate resistor.

2. The ESD protection circuit of claim 1, wherein the first substrate resistor comprises an intrinsic resistance of a P-substrate of the protection circuit.

3. The ESD protection circuit of claim 1, wherein the first shunt resistor is selected from the group comprising a fixed resistor and a variable resistor.

4. The ESD protection circuit of claim 1, wherein the first trigger device comprises a grounded-gate NMOS device.

5. The ESD protection circuit of claim 1, wherein during normal powered operation of the IC, the first gate of the SCR is pulled to approximately ground potential via the first shunt resistor, and wherein during non-powered operation of the IC and after activation of said trigger device during an ESD event, the first gate is approximately 0.7 volts.

6. The ESD protection circuit of claim 1, wherein during normal powered operation of the IC, the first gate of the SCR is pulled to approximately ground potential via the first substrate resistor, and wherein during non-powered operation of the IC and after activation of said trigger device during an ESD event, the first gate is approximately 0.7 volts.

7. The ESD protection circuit of claim 1, further comprising:

at least one diode, coupled in a forward conduction direction from a cathode of the SCR to ground.

8. The ESD protection circuit of claim 3, further comprising:

a first latch-up (LU) control circuit, for coupling between said supply line and ground, and further coupled to said first gate via said first shunt resistor.

9. The ESD protection circuit of claim 8, wherein the first latch-up (LU) control circuit is further coupled to a reference supply line, which is coupled to ground via parasitic capacitance.

10. The ESD protection circuit of claim 1, further comprising:

a second trigger device coupled from a second gate of the SCR to ground.

11. The ESD protection circuit of claim 10, further comprising:

a third resistor for coupling from the supply line to the second gate.

12. The ESD protection circuit of claim 11, further comprising a second shunt resistor for coupling from the supply line to the second gate, wherein said second resistor is selected from the group consisting of a fixed and a variable resistor.

13. The ESD protection circuit of claim 12, further comprising:

a second latch-up (LU) control circuit, for coupling between said supply line and ground, and further coupled to said second gate via said second shunt resistor.

14. The ESD protection circuit of claim 13, wherein the second latch-up (LU) control circuit is further coupled to a reference supply line, which is coupled to ground via parasitic capacitance.

15. The ESD protection circuit of claim 1, wherein the SCR further comprises a plurality of SCR fingers having a respective plurality of first gates, said ESD protection circuit further comprising:

a first latch-up (LU) control circuit for coupling between said supply line and ground, and further coupled to each first gate of each SCR finger via said first shunt resistor.

16. The ESD protection circuit of claim 15, wherein the SCR further comprises a respective plurality of second gates, said ESD protection circuit further comprising:

a second shunt resistor for coupling between said supply line and said plurality of second gates;

a second latch-up (LU) control circuit for coupling between said supply line and ground, and for further coupling to each second gate of each SCR finger via said second shunt resistor.

18. The ESD protection circuit of claim 17, wherein said first gate control circuit comprises:

a first NMOS transistor having the drain coupled to the first gate and the source coupled to ground; and

a first inverter having an input and an output, wherein the output of said inverter is coupled to the gate of the first NMOS transistor and the common control circuit; and

wherein the first NMOS transistor provides a variable shunt element for the first trigger gate of the SCR.

19. The ESD protection circuit of claim 18, wherein said first inverter comprises:

a first PMOS transistor and a second NMOS transistor, and said first PMOS transistor and second NMOS transistor are serially coupled between the supply line and ground; and

the drains of said NMOS and PMOS transistors form an output of the inverter, wherein the output is connected to the gate of said first NMOS transistor.

20. The ESD protection circuit of claim 19, wherein said common control circuit comprises:

a third NMOS transistor having the drain for coupling to the supply line, and the source coupled to an input of the inverter circuit;

a first pull-down resistor for coupling between the input of the inverter circuit and ground;

a trigger element for coupling between the supply line and the gate of the third NMOS transistor; and

a second pull-down resistor, for coupling between the gate of the third NMOS transistor and ground.

21. The ESD protection circuit of claim 20, wherein said trigger element is a device selected from the group consisting of a capacitor, a Zener diode coupled in a reverse bias direction between the supply line and the gate of the third NMOS transistor, and a grounded-gate NMOS transistor.

22. The ESD protection circuit of claim 20, further comprising:

a second trigger device for coupling from a second gate of the SCR to ground; and

a second gate control circuit for coupling between said supply line and said second gate, and further coupled to said common control circuit.

23. The ESD protection circuit of claim 21, wherein said second gate control circuit comprises a PMOS transistor having the source for coupling to said supply line, the drain coupled to said second trigger gate of the SCR, and the gate of the PMOS transistor coupled to the common control circuit.

24. The ESD protection circuit of claim 19, wherein said common control circuit comprises:

a second inverter having a second PMOS transistor serially coupled to a third NMOS transistor, said second inverter for coupling between the supply line and ground, and said inverter having an input and an output;

a pull-up resistor coupled to the input of said second inverter and the supply line; and

a fourth pull-down NMOS transistor having the drain coupled to the input of said second inverter and the source to ground, said gate of said fourth pull-down NMOS transistor coupled to the first gate of said SCR.

26. The ESD protection circuit of claim 25, further comprising:

a second trigger device coupled from a second gate of the SCR to ground.

27. The ESD protection circuit of claim 25, further comprising:

a PMOS transistor, having the source for coupling a supply line having a potential greater than the protected supply line, and the drain coupled to the second gate; and

the gate of said PMOS transistor for coupling to a supply line having a potential less than the potential of the supply line connected to the source of said PMOS.

17. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

a silicon controlled rectifier (SCR), for coupling between a supply line of the IC and ground;

a first trigger device for coupling from the supply line to a first gate of the SCR;

a first shunt resistor for coupling between the first gate and ground;

a first gate control circuit, for coupling between the supply line and ground, and for further coupling to the first gate of the SCR; and

a common control circuit, for coupling between the supply line and ground, and for further coupling to the first gate control circuit.

25. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

a silicon controlled rectifier (SCR), for coupling between a protected supply line of the IC and a ground;

a first trigger device, for coupling from the said protected supply line to a first gate of the SCR;

a first shunt resistor coupled between the first gate and ground; and

a NMOS transistor, having the drain and source respectively, coupled between the first gate and ground, and the gate of said NMOS transistor for coupling to a supply line of the IC having a potential different from the potential of the protected supply line of the IC.

28. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

an SCR, having a respective GGNMOS transistor coupled to a first gate of said SCR, and a SGPMOS transistor coupled to a second gate of said SCR, said SCR, GGNMOS and SGPMOS transistors arranged in slices, further comprising;

an N-well;

a P-well positioned adjacent to said N-well and forming a junction therebetween;

a first plurality of P+ regions interspersed in said N-well forming an anode of said SCR, for coupling to a protected supply line, and a source of said SGPMOS transistor;

a first plurality of N+ regions interspersed in said P-well forming a cathode of said SCR, said first plurality of N+ regions for coupling to ground, and a source of said GGNMOS transistor, said first plurality of P+ and N+ regions being aligned and forming SCR and MOS transistor slices;

a second plurality of N+ regions interspersed in said N-well between said first plurality of P+ regions and forming a plurality of second gates and coupled to said anode;

a second plurality of P+ regions interspersed in said P-well between said first plurality of N+ regions and forming a plurality of first gates and coupled to said cathode; and

a third plurality of P+ regions interspersed in said N-well and separated from said first plurality of P+ regions by a respective first plurality of perpendicular gate regions, said third plurality of P+ regions forming a drain of said SGPMOS transistor;

said first plurality of perpendicular gates coupled to said anode, said third plurality of P+ regions coupled to said cathode; and

a third plurality of N+ regions interspersed in said P-well and separated from said second plurality of N+ regions by a respective second plurality of perpendicular gate regions, said third plurality of N+ regions forming a drain of said GGNMOS transistor;

said second plurality of perpendicular gates coupled to said cathode, said third plurality of N+ regions coupled to said anode.

29. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

an N-well;

a P-well positioned adjacent to said N-well and forming a junction therebetween;

a first P+ region, forming a drain of a SGPMOS transistor disposed in said N-well, said first P+ region for coupling to ground;

a second P+ region forming an emitter of a PNP transistor of an SCR and forming a source of SGPMOS disposed in said N-well and parallel to said first P+ region, said second P+ region for coupling to a supply line of the IC;

a first gate region of said SGPMOS disposed parallel and between said first and second P+ regions, and over said N-well, said first gate region for coupling to the supply line of the IC;

a first N+ region, forming the second gate of an SCR disposed in said n-well and parallel to said first and second P+ regions, said first N+ region for coupling to the supply line of the IC;

a second N+ region forming an emitter of an NPN transistor of said SCR and forming a source of a GGNMOS disposed in said P-well, Said second N+ region for coupling to ground;

a third N+ region, forming a drain of a GGNMOS transistor disposed in said P-well parallel to said second N+ region, said third N+ region for coupling to the supply line of the IC;

a second gate region disposed in parallel and between said second and third N+ regions, over said P-well, said gate region for coupling to ground; and

a third P+ region, forming a second gate of the SCR disposed in said P-well and parallel to said second and third N+ regions, said third P+ region for coupling to ground.

30. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

an SCR, having a respective GGNMOS transistor having a parasitic NPN transistor having a the base coupled to a first gate of said SCR, said SCR and GGNMOS transistor arranged in slices, further comprising;

an N-well;

a P-well, positioned adjacent to said N-well and forming a junction therebetween;

a first plurality of P+ regions interspersed in said N-well, and forming an emitter of a PNP transistor of said SCR and adapted for coupling to a supply line of the IC;

a first plurality of N+ regions interspersed in said N-well, and forming a drain contact region of said GGNMOS transistor, said first plurality of N+ regions for coupling to the supply line of the IC,

a second N+ region, disposed over said junction of said N-well and P-well, and coupling to said first plurality of N+ regions and forming drain of said GGNMOS transistor;

a third N+ region, forming an emitter of the NPN transistor and the source of said GGNMOS transistor, disposed in said P-well and parallel to said second N+ region, said third N+ region for coupling to ground;

a gate region, disposed in parallel and between said second and third N+ regions, over said P-well, and for coupling to ground;

a second P+ region, forming said first gate of said SCR, disposed in said P-well and parallel with said second and third N+ regions, said second P+ region for coupling to ground.

31. The ESD protection circuit of claim 30, further comprising:

a polysilicon layer disposed over said N-well and between the first P+ regions and the first interspersed N+ regions.

32. The ESD protection circuit of claim 30, wherein portions of the second and third N+ regions facing the gate region, and the gate region are silicide blocked.

33. The ESD protection circuit of claim 30, wherein said first interspersed N+ regions and third N+ region are segmented and resistor-ballasted, and said first and second P+ regions, said first, second, and third N+ regions, and said gate region are fully silicided.

34. The ESD protection circuit of claim 30, further comprising a second N-well disposed below a portion of said third N+ region facing the second P+ region

36. The ESD protection circuit of claim 35, wherein a portion of the second and third N+ regions facing the gate region, and the gate region are silicide blocked.

35. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

an SCR having a respective GGNMOS transistor coupled to a first gate of said SCR, said SCR and GGNMOS transistor arranged in slices, further comprising;

an N-well having interdigited fingers;

a P-well having interdigited fingers, interlocking with said N-well fingers and forming a junction therebetween;

a first plurality of P+ regions disposed in each of the interdigitated fingers of said N-well, and forming an emitter of a PNP transistor of said SCR, and adapted for coupling to a supply line of the IC, said;

a first plurality of N+ regions disposed in each of the interdigitated fingers of said P-well and forming a drain of said GGNMOS transistor, said first plurality of N+ regions coupled to the supply line,

a second N+ region disposed in said P-well and forming an emitter of the NPN transistor and the source of said GGNMOS transistor, said second N+ regions for coupling to ground;

a gate region, disposed in parallel and between said first plurality of interspersed N+ regions and the second N+ region, over said P-well, and adapted for coupling to ground;

a second P+ region, forming said first gate, disposed in said P-well and parallel with said second N+ region, and adapted for coupling to ground; and

a plurality of third P+ regions disposed in each of the interdigitated fingers of said P-well and between said first plurality of P+ regions and said first plurality of N+ regions, each third P+ region coupled to the gate region forming a local substrate pick-up.

37. An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry, comprising:

an SCR comprising

a N-well;

a P-well positioned adjacent to said N-well and forming a junction therebetween;

a first plurality of P+ regions interspersed in said N-well forming an anode;

a first plurality of N+ regions interspersed in said P-well forming a cathode and aligned with said first plurality of P+ regions, each said first N+ region and first P+ region having a first length in a range from 0.16 to 10 micrometers;

a second plurality of P+ regions interspersed in said P-well between said first plurality of N+ regions and forming a plurality of first gates,

a second plurality of N+ regions interspersed in said N-well between said first plurality of P+ regions and forming a plurality of second gates;

each said second N+ region and second P+ region having a second length in a range of 0.2 to 2 micrometers; and

wherein a distance between the first P+ region and the second N+ region are in a range from 0.12 to 1.2 micrometers, and a distance between the first N+ region and the second P+ regions are in a range from 0.12 to 1.2 micrometers.