Probe structure for testing semiconductor devices and method for fabricating the same

• US 20020153911A1
• Filed: 04/18/2002
• Published: 10/24/2002
• Est. Priority Date: 04/18/2001
• Status: Active Grant

• Current Assignee: WILL Technology Co., Ltd.
• Original Assignee: IC Mems, Inc.
• Inventors: Park, Sangjun, Cho, Dong-il
• Granted Patent: US 6,724,204 B2
• Time in Patent Office: Days
• US Class Current: 324/754
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips

Abstract

Disclosed are a probe structure for testing semiconductor devices and a method for fabricating the probe structure. The fabricated probe structure of the present invention satisfies the high density, the uniformity of size, height and spacing, and the integration of elements. The probe structure of the present invention solves the conventional problems such as long fabrication time of the probe structure, difficulty in finely controlling the structure of the probe structure, complexity of the whole process, mechanical instability of the products, and difficulty in uniformly assembling a plurality of the probe structures. Additionally, the probe structure of the present invention solves several problems caused in an actual testing step of the semiconductor devices, for instance, long testing time of the semiconductor device, difficulty in providing the sufficient contact force between the probe structure and the semiconductor device, and having to specially design the test pads of the semiconductor device.

Claims

1. A probe structure for testing semiconductor devices, said probe structure comprising:

a base substrate;

a protrusion formed integrally with the base substrate, protruded from the upper surface of the base substrate at a designated angle, and extending along the upper surface of the base substrate;

probe beams branching off from the protrusion, positioned above the upper surface of the base substrate, and extending along the upper surface of the base substrate in a different direction from the direction of the extension of the protrusion; and

probe tips rested on the ends of the probe beams and protruded from the probe beam in a direction perpendicular to the the upper surface of the base substrate.

2. The probe structure for testing semiconductor devices according to claim 1, wherein the base substrate, the protrusion, the probe beams, and the probe tips are integrally made of the same material.

3. The probe structure for testing semiconductor devices according to claim 2, wherein the base substrate, the protrusion, the probe beams, and the probe tips are integrally made of one selected from the group consisting of a single crystalline bulk substrate, a SOI (Silicon On Insulator) bulk substrate, and a SOG (Silicon On Glass) bulk substrate.

4. The probe structure for testing semiconductor devices according to claim 3, wherein the single crystalline bulk substrate, the SOI bulk substrate, and the SOG bulk substrate are oriented in the direction of the (111) plane.

5. A method for fabricating a probe structure for testing semiconductor devices, said method comprising the steps of:

forming a plurality of probe tips with pointed tip by patterning one surface of a bulk substrate at a designated depth; and

integrally forming a base substrate, a plurality of probe beams positioned above the base substrate, and a protrusion formed integrally with the probe beams by patterning both sides of the surface of the bulk substrate including probe tips.

6. The method for fabricating a probe structure for testing semiconductor devices according to claim 5, wherein the step of forming a plurality of the probe tips with pointed tip comprises the sub-steps of:

depositing an insulation layer on the surface of the bulk substrate and patterning said insulation layer so that the insulation layer is left on a predetermined area of the surface of the bulk substrate;

isotropically etching the bulk substrate to a designated depth using the patterned insulation layer as a mask; and

anisotropically etching the bulk substrate to a designated depth using the patterned insulation layer as a mask.

7. The method for fabricating a probe structure for testing semiconductor devices according to claim 5, wherein the step of integrally forming the base substrate, a plurality of the probe beams positioned above the base substrate, and the protrusion formed integrally with the probe beams comprises the sub-steps of:

depositing an insulation layer on the surface of the bulk substrate so that the probe tips are covered, and patterning the insulator layer so that the parts of both sides of the surface of the bulk substrate are exposed;

anisotropically etching both sides of the surface of the bulk substrate to a designated depth using the patterned insulation layer as a mask;

depositing a passivation layer on the surface of the bulk substrate so that the patterned insulation layer and the sidewalls of the etched bulk substrate are covered;

patterning the passivation layer so that both sides of the surface of the bulk substrate except for the sidewalls are exposed;

anisotropically etching the exposed both sides of the bulk substrate to a designated depth; and

patterning the bulk substrate with the probe tips using a wet etching solution, thereby forming a trench dug into the bulk substrate below the probe tips.

8. The method for fabricating a probe structure for testing semiconductor devices according to claim 7, wherein said wet etching solution is an alkaline solution with a selective etch rate according to the crystalline direction of the bulk substrate.

9. The method for fabricating a probe structure for testing semiconductor devices according to claim 8, wherein said alkaline solution is one selected from the group consisting of KOH solution, TMAH (tetramethylammonium hydroxide) solution, NaOH solution and EDP (ethylene diamine pyrocatechol) solution.