Display device and method of driving a display device

• US 20020154151A1
• Filed: 04/10/2002
• Published: 10/24/2002
• Est. Priority Date: 04/20/2001
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Granted Patent: US 7,027,074 B2
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: H10K 50/841 Self-supporting sealing arrangements
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/8722 Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 59/873 Encapsulations

Abstract

Write in of lower significant bits of a digital video signal to a memory is eliminated by a memory controller of a signal control circuit in a display device during a second display mode in which the number of gray scales is reduced, as compared to a first display mode. Further, read out of the lower significant bits of the digital video signal from the memory is also eliminated. The amount of information of digital image signals input to a source signal line driver circuit is reduced. Corresponding to this operation, a display controller functions to make start pulses and clock pulses input to each driver circuit have a lower frequency, and write in periods and display periods of sub-frame periods participating in display are set longer.

Claims

1. A display device comprising:

a means for dividing one frame period into a plurality of sub-frame periods;

means for selecting a light emitting state or a non-light emitting state in each of the plurality of sub-frame periods in accordance with a n-bit digital signal (where n is a natural number) input to a pixel;

means for selecting a first display mode or a second display mode;

means for inputting the n-bit digital signal to the pixel as a first digital image signal during the one frame period in the first display mode;

means for inputting a first bit digital signal to a m-th bit digital signal (where m is a natural number less than n) of the n-bit digital signal to the pixel as a second digital image signal during the one frame period in the second display mode; and

means for changing a length of each of the m sub-frame periods in the second display mode which are respectively corresponding to the second digital image signal, to q times a length of each of the m sub-frame periods in the first display mode which are respectively corresponding to the first bit digital signal to the m-bit digital signal of the first digital image signal (where q is a number greater than

     1).

2. A display device according to claim 1 further comprising:

a pixel portion comprising the pixel as one of pixels in a matrix state;

a driver circuit for inputting the first digital image signal and the second digital image signal to the pixel; and

means for changing the second frequency of the driver circuit in the second display mode to 1/q times the first frequency in the first display mode.

3. A display device according to claim 1 further comprising:

a pixel portion comprising the pixel in a matrix state;

a memory;

means for storing the first digital image signal in the memory in the first display mode and for storing the second digital image signal in the memory in the second display mode; and

means for changing the second frequency in the second display mode for reading out the second digital image signal from the memory to 1/q times the first frequency in the first display mode.

4. A display device according to claim 1 further comprising means for making brightness of the pixel lower in the second display mode than in the first display mode.

5. A display device according to claim 1 further comprising:

a light emitting element in the pixel; and

means for changing an electric potential applied to an electrode of the light emitting element to make brightness of the light emitting element lower in the second display mode than in the first display mode.

6. A display device according to claim 1, the display device is selected from the group consisting of a computer, a television, and a video camera.

7. A method of driving a display device comprising:

dividing one frame period into a plurality of sub-frame periods;

selecting a light emitting state or a non-light emitting state in each of the plurality of sub-frame periods in accordance with a n-bit digital signal (where n is a natural number) input to a pixel;

selecting a first display mode or a second display mode;

inputting the n-bit digital signal to the pixel as a first digital image signal during the one frame period in the first display mode; and

inputting a first bit digital signal to a m-th bit digital signal (where m is a natural number less than n) of the n-bit digital signal to the pixel as a second digital image signal during the one frame period in the second display mode,

wherein a length of each of the m sub-frame periods in the second display mode which are respectively corresponding to the second digital image signal, is q times a length of each of the m sub-frame periods in the first display mode which are respectively corresponding to the first bit digital signal to the m-bit digital signal of the first digital image signal (where q is a number greater than

     1).

8. A method of driving a display device according to claim 7,

wherein a pixel portion comprises the pixel one of pixels in a matrix shape, and

wherein a driver circuit inputs the first digital image signal and the second digital image signal to the pixel, and

wherein the second frequency of the driver circuit in the second display mode is 1/q times the first frequency in the first display mode.

9. A method of driving a display device according to claim 7,

wherein a pixel portion comprises the pixel as one of pixels in a matrix state,

wherein the first digital image signal is stored in a memory in the first display mode and the second digital image signal is stored in the memory in the second display mode;

and

wherein the second frequency in the second display mode for reading out the second digital image signal from the memory is 1/q times the first frequency in the first display mode.

10. A method of driving a display device according to claim 7, wherein brightness of the pixel is lower in the second display mode than in the first display mode.

11. A method of driving a display device according to claim 7,

wherein the pixel comprises a light emitting element, and

wherein an electric potential applied to an electrode of the light emitting element to make brightness of the light emitting element lower in the second display mode than the in the first display mode.

12. An electronic equipment which uses the method of driving the display device according to claim 7.

14. A display device according to claim 13,

wherein a gray scale controller signal is input to the variable frequency divider circuit, and

wherein frequency of each of the clock pulse for the source signal line driver circuit, the start pulse for the source signal line driver circuit, the clock pulse for the gate signal line driver circuit, and the start pulse for the gate signal line driver circuit are made lower in the second display mode compared to those in the first display mode.

15. A display device according to claim 13,

wherein the display controller comprises an electric power source controller circuit used for the light emitting element, and

wherein, in accordance with a gray scale controller input to the electric power source controller circuit used for the light emitting element, signal the electric potential of the opposing electrode of the light emitting element is changed so that the brightness of light emitted from the light emitting element in a light emitting state becomes less in the display period corresponding to the t-bit in the second display mode, than that in the display period corresponding to the t-bit in the first display mode (where t is a natural number less than m).

16. A display device according to claim 13, wherein the display device is selected from the group consisting of a video camera, a television, and a computer.

13. A display device comprising:

a signal control circuit;

a display controller; and

a display,

wherein the display comprises a source signal line driver circuit, a gate signal line driver circuit, and a plurality of pixels,

wherein each of the plurality of pixels comprises a light emitting element,

wherein the signal control circuit comprises a CPU, a memory for storing a digital video signal and outputting a digital image signal to the display, and a memory controller,

wherein the display controller is electrically connected to the source signal line driver circuit for inputting a clock pulse for the source signal line driver circuit and a start pulse for the source signal line driver circuit, and to the gate signal line driver circuit for inputting a clock pulse for the gate signal line driver circuit and a start pulse for the gate signal line driver circuit,

wherein display of an image is performed by switching between a first display mode in which gray scales are expressed by using first bit to n-th bit (where n is a natural number) of the digital video signal, and a second display mode in which gray scales are expressed by first to a m-bit (where m is a natural number less than n) of the digital video signal,

wherein, in the first display mode, the memory controller writes the first bit to n-th bit of the digital video signal to the memory from the CPU, and outputs the first bit to n-th bit of the digital video signal written into the memory to the source signal line driver circuit as the digital image signal,

wherein, in the second display mode, the memory controller writes the first bit to m-bit of the digital signal to the memory from the CPU, and outputs writes the first bit to m-bit of the digital video signal written into the memory to the source signal line driver circuit as the digital image signal, and

wherein the display controller lowers frequency of each of the clock pulse for the source signal line driver circuit, the start pulse for the source signal line driver circuit, the clock pulse for the gate signal line driver circuit, and the start pulse for the gate signal line driver circuit in the second display mode compared to those in the first display mode.