Communications architecture for storage-based devices

• US 20020154633A1
• Filed: 11/07/2001
• Published: 10/24/2002
• Est. Priority Date: 11/22/2000
• Status: Abandoned Application

• Current Assignee: Universal Connectivity Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: Universal Connectivity Technologies Inc. (Wi-LAN Inc.)
• Inventors: Kong, Shing, Lee, David D., Shin, Yeshik, Jeong, Deog-Kyoon
• Application Number:
  US10/035,591
• Publication Number:
  US 20020154633A1
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/245 using preemption
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 47/365 Dynamic adaptation of the packet size

Abstract

A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Claims

1. A communications architecture for communicating between hosts and data store devices, the communications architecture comprising:

a plurality of hosts, each host having a communications interface with a serial communications link;

a plurality of data store devices, each data store device having a communications interface with a serial communications link; and

a switching network having communications interfaces with serial communications links for establishing communications paths between hosts and data store devices

wherein the communications architecture supports control packets and data packets, the control packets and data packets having headers with different formats, supports data packets having a variable length, and supports preemption of data packets by control packets.

2. The communications architecture of claim 1 wherein the hosts, data store devices, and switching network form a storage area network.

3. The communications architecture of claim 1 wherein the data store devices are disk-based.

4. The communications architecture of claim 1 wherein the data store devices are block-oriented.

5. The communications architecture of claim 1 wherein the communications architecture supports dynamic segmentation of data packets.

6. The communications architecture of claim 5 wherein the communications architecture supports merging of segmented data packets.

7. The communications architecture of claim 1 wherein multiple data packets form a transaction, the data packets having an order within the transaction, and wherein the communications architecture ensures that the data store devices receive data packets of a transaction in order.

8. The communications architecture of claim 7 wherein the communications architecture does not ensure that the hosts receive data packets in order of transmission.

9. The communications architecture of claim 1 wherein when an error is detected during processing of a transaction, the host that initiated the transaction is notified so that the initiating host can handle the error.

10. The communications architecture of claim 9 wherein when an error is detected by the switching network, the switching network forwards an error message to the initiating host.

11. The communications architecture of claim 9 wherein the error is at a physical layer.

12. The communications architecture of claim 9 wherein the error is at a link layer.

13. The communications architecture of claim 9 wherein the error is at a transport layer.

14. The communications architecture of claim 1 wherein the switching network upon detecting an error during processing of a packet transmitted from a data store device to host, notifies the host of the error without notifying the data store device of the error.

15. The communications architecture of claim 14 wherein the switching network does not attempt to correct errors.

16. The communications architecture of claim 1 wherein the switching network asymmetrically processes packets received from the hosts and packets received from the data store devices.

17. The communications architecture of claim 16 wherein the asymmetric processing includes handling of errors.

18. The communications architecture of claim 16 wherein the asymmetric processing includes ordering of packets within a transaction.

20. The communications architecture of claim 19 wherein the asymmetric processing of packets includes ensuring that packets of a transaction transmitted by a host are received in order by a data store device and not ensuring that packets of a transaction transmitted by a data store device are received in order by a host.

21. The communications architecture of claim 20 wherein packets of a transaction are guaranteed to be transmitted along the same path from a host to a data store device and not guaranteed to be transmitted along the same path from a data store device to a host.

22. The communications architecture of claim 20 wherein packet-level load balancing is performed on packets transmitted from a data store device to a host, but not performed on packets transmitted from a host to a data store device.

23. The communications architecture of claim 19 wherein the asymmetric processing of packets includes when an error is detected during transmission of a packet from a host to a data store device notifying the host of the error so that the host can handle the error and when an error is detected during transmission of a packet from a data store device to a host notifying the host of the error so that the host can handle the error.

24. The communications architecture of claim 23 wherein only the host that receives the notification performs error handling.

25. The communications architecture of claim 19 wherein the hosts, the data store devices, and the switching network form a storage area network.

26. The communications architecture of claim 19 wherein the data store devices are disk-based.

27. The communications architecture of claim 19 wherein the communications architecture supports control packets and data packets, the control packets and data packets having headers with different formats.

28. The communications architecture of claim 19 wherein the communications architecture supports data packets having a variable number of blocks.

29. The communications architecture of claim 19 having control packets and data packets and wherein transmission of data packets can be preempted by control packets.

19. A communications architecture for communicating between hosts and data store devices, the communications architecture comprising:

a plurality of hosts, each host having a communications interface with a serial communications link;

a plurality of data store devices, each data store device having a communications interface with a serial communications link and being block-oriented; and

a switching network having communications interfaces with serial communications links for establishing communication s paths between hosts and data store devices, the switching network for asymmetrically processing packets transmitted by hosts and packets transmitted by data store devices.

30. A network for transmitting data between hosts and data store devices, the data store devices being block-oriented, the switching network comprising:

a plurality of communications interfaces to hosts,

a plurality of communications interfaces to data store devices; and

a path component for establishing communications paths between hosts and data store devices, for transmitting data packets and control packets, the control packets and data packets having headers with different formats, the data packet having a variable length, and for preempting transmission of data packets to transmit control packets.

31. The network of claim 30 wherein the hosts, data store devices, and network form a storage area network.

32. The network of claim 30 wherein the path component dynamically segments data packets.

33. The network of claim 32 wherein the path component dynamically merges segmented data packets.

34. The network of claim 32 wherein multiple data packets form a transaction, the data packets having an order within the transaction, and wherein the path component ensures that the data store devices receive data packets of a transaction in order.

35. The network of claim 34 wherein the path component does not ensure that the hosts receive data packets of a transaction in order.

36. The network of claim 30 wherein when an error is detected by the path component during processing of a transaction, the host that initiated the transaction is notified so that the initiating host can handle the error.

37. The network of claim 36 wherein the path component does not attempt to correct errors.

38. The network of claim 30 wherein the path component asymmetrically processes packets received from the hosts and packets received from the data store devices.

39. The network of claim 38 wherein the asymmetric processing includes handling of errors.

40. The network of claim 38 wherein the asymmetric processing includes ordering of packets within a transaction.