EMI and noise shielding for multi-metal layer high frequency integrated circuit processes

• US 20020155655A1
• Filed: 04/18/2001
• Published: 10/24/2002
• Est. Priority Date: 04/18/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pon, Harry Q.
• Granted Patent: US 6,800,918 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A circuit element that may generate or be affected by noise or electromagnetic interference may be substantially surrounded by one or more encircling plugs. The encircling plug may be closed by an interconnection layer. The plug may be grounded to reduce the electromagnetic interference or noise generated by or coupled to said passive circuit element.

Claims

1. A method comprising:

forming a trench around an electrical component;

filling said trench with a conductive material; and

forming an interconnection layer coupled to said conductive material.

2. The method of claim 1 including forming said trench between said interconnection layer and a semiconductor structure.

3. The method of claim 1 including forming said trench between a pair of interconnection layers.

4. The method of claim 3 including forming a first trench between a first pair of interconnection layers and a second trench between a second pair of interconnection layers and positioning a passive circuit element between said trenches.

5. The method of claim 1 including grounding said material.

6. The method of claim 1 including positioning a passive circuit element within an enclosure formed by said material and layer.

7. The method of claim 6 including forming an opening in said material to allow an electrical connection to said passive circuit element.

8. The method of claim 6 including connecting said passive circuit element to other devices through a buried contact.

9. The method of claim 1 including electrically coupling said material and said interconnection layer.

10. The method of claim 6 including forming a flat spiral inductor to act as said passive circuit element over said semiconductor structure.

11. The method of claim 10 including forming a resistor and capacitor.

12. The method of claim 1 including forming said material over a guard ring.

14. The circuit of claim 13 wherein said trench substantially encircles said passive circuit element.

15. The circuit of claim 14 wherein said material includes an opening for an electrical connection to said passive circuit element.

16. The circuit of claim 13 wherein said passive circuit element is a flat spiral inductor.

17. The circuit of claim 13 including first, second and third interconnection layers, said passive circuit element formed in said second interconnection layer and a pair of metal-filled trenches extending between said first and second interconnection layers and said third and second interconnection layers.

18. The circuit of claim 13 wherein said trench extends from said interconnection layer to said substrate.

19. The circuit of claim 13 wherein said material is grounded.

20. The circuit of claim 13 including a buried contact which couples said passive circuit element under said material.

21. The circuit of claim 13 wherein said material and said interconnection layer are electrically coupled.

13. An integrated circuit comprising:

a semiconductor substrate;

an interconnection layer positioned over said substrate;

a passive circuit element between said substrate and said interconnection layer; and

a trench that encircles said passive circuit element, said trench filled with a conductive material.

22. A method comprising:

forming an integrated passive circuit element; and

substantially enclosing said element using a trench filled with a conductive material.

23. The method of claim 22 including forming an interconnection layer coupled to said material.

25. The circuit of claim 23 wherein said material couples to a guard ring connection layer to bias said guard ring.

26. The circuit of claim 24 including a metal one layer over said substrate, said material electrically coupled to said guard ring and said metal one layer.

27. The circuit of claim 24 wherein said guard ring completely surrounds said active circuit element.

28. The circuit of claim 27 wherein said trench completely surrounds said active circuit element.

29. The circuit of claim 24 wherein said active circuit element includes a transistor.

30. The circuit of claim 24 wherein said active circuit element is enclosed in a shield over the substrate, said shield formed by said material and an overlying metal layer.

24. An integrated circuit comprising:

a semiconductor substrate;

an active circuit element formed in said substrate;

a guard ring encircling said active circuit element formed in said substrate; and

a trench filled with a conductive material coupled to said guard ring.