Gate delay calculation apparatus and method thereof using parameter expressing RC model source resistance value

• US 20020156610A1
• Filed: 04/29/2002
• Published: 10/24/2002
• Est. Priority Date: 03/04/1997
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Komoda, Michio, Kuriyama, Shigeru
• Application Number:
  US10/133,672
• Publication Number:
  US 20020156610A1
• Time in Patent Office: Days
• US Class Current: 703/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A gate delay calculation apparatus includes an R_s parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continues time function, an R_s determination portion for selectively extracting the parameter prestored in the R_s parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by R_s determination portion and the output load model.

Claims

1. A gate delay calculation apparatus comprising:

storage means for prestoring in advance a parameter expressing a source resistance value of an RC model as a continuous time function;

extract means for selectively extracting the parameter prestored in said storage means from an amount of input waveform gradient and an output load model; and

gate delay determination means for calculating gate delay based on a source resistance value expressed by the parameter extracted by said extract means and said output load model.

2. The gate delay calculation apparatus according to claim 1, wherein said gate delay determination means calculates an output voltage based on the source resistance value expressed by the parameter extracted by said extract means and said output load model, and determines a time at which said output voltage attains a prescribed value as gate delay.

3. The gate delay calculation apparatus according to claim 1, further comprising input waveform determination means for determining an input waveform for a wire delay calculation apparatus based on the source resistance value expressed by the parameter extracted by said extract means and said output load model.

4. The gate delay calculation apparatus according to claim 3, wherein said input waveform determination means calculates an output voltage based on the source resistance value expressed by the parameter extracted by said extract means and said output load model, and determines a difference between a time at which said output voltage attain a first prescribed value and the time at which said output voltage attains a second prescribed value as an input waveform.

5. A gate delay calculation method comprising:

the step of selectively determining a parameter expressing a source resistance value of an RC model as a continuous time function from an amount of input waveform gradient and an output load model; and

the step of calculating gate delay based on said source resistance value expressed by the parameter and said output load model.

6. The gate delay calculation method according to claim 5, wherein said step of calculating gate delay includes the step of calculating an output voltage based on said source resistance value expressed by the parameter and said output load model, and the step of determining a time at which said output voltage attains a prescribed value as gate delay.

7. The gate delay calculation method according to claim 5 further comprising the step of determining an input waveform for a wire delay calculation apparatus based on said source resistance value expressed by the parameter and said output load model.

8. The gate delay calculation method according to claim 7 wherein said step of determining input waveform includes:

the step of calculating an output voltage based on said source resistance value expressed by the parameter and said output load model;

the step of calculating a first time at which said output voltage attains a first prescribed value;

the step of calculating a second time at which said output voltage attains a second prescribed value; and

the step of determining a difference between said first and second times as an input waveform.