TCP/IP offload network interface device
First Claim
1. A method, comprising:
- maintaining a set of communication control blocks (CCBs), some of the set of CCBs being maintained in a static random access memory (SRAM), others of the set of CCBs being maintained in a dynamic random access memory (DRAM), wherein a first plurality of the set of CCBs is under control of a network interface device, and wherein a second plurality of the set of CCBs is under control of a processing device, the processing device being coupled to the network interface device, the processing device executing a network protocol stack;
receiving a TCP/IP packet onto the network interface device from a network, the TCP/IP packet including a data portion and a header portion;
using a content addressable memory (CAM) on the network interface device to detenmine that the TCP/IP packet is associated with one of the first plurality of CCBs;
detennining on the network interface device that said one CCB is stored in the DRAM and transferring said one CCB into the SRAM; and
transferring the data portion of the TCP/IP packet from the network interface device and into a destination without transferring the header portion of the TCP/IP packet into the destination, the destination having been determined by the processing device, wherein the network protocol stack executing on the processing device performs substantially no TCP protocol processing on the TCP/IP packet.
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Accused Products
Abstract
A system for protocol processing in a computer network has a TCP/IP Offload Network Interface Device (TONID) associated with a host computer. The TONID provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The TONID also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the TONID to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the TONID as a communication control block (CCB) that can be passed back to the host for message processing by the host. The TONID contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.
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Citations
20 Claims
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1. A method, comprising:
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maintaining a set of communication control blocks (CCBs), some of the set of CCBs being maintained in a static random access memory (SRAM), others of the set of CCBs being maintained in a dynamic random access memory (DRAM), wherein a first plurality of the set of CCBs is under control of a network interface device, and wherein a second plurality of the set of CCBs is under control of a processing device, the processing device being coupled to the network interface device, the processing device executing a network protocol stack;
receiving a TCP/IP packet onto the network interface device from a network, the TCP/IP packet including a data portion and a header portion;
using a content addressable memory (CAM) on the network interface device to detenmine that the TCP/IP packet is associated with one of the first plurality of CCBs;
detennining on the network interface device that said one CCB is stored in the DRAM and transferring said one CCB into the SRAM; and
transferring the data portion of the TCP/IP packet from the network interface device and into a destination without transferring the header portion of the TCP/IP packet into the destination, the destination having been determined by the processing device, wherein the network protocol stack executing on the processing device performs substantially no TCP protocol processing on the TCP/IP packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19, 20)
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14. A network interface device that is coupled to a processing device, the processing device executing a protocol stack, the network interface device comprising:
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an amount of SRAM, the SRAM storing a first plurality of communication control blocks (CCBs) that are under control of the network interface device;
an amount of DRAM, the DRAM storing a second plurality of CCBs that are under control of the network interface device;
specialized hardware that analyzes a TCP/IP packet received onto the network interface device from a network, the TCP/IP packet comprising a data portion and a header portion, the specialized hardware generating a summary from the TCP/IP packet;
a processor that uses the summary and a content addressable memory to determine whether the TCP/IP packet can be processed via a fast-path by the network interface device as opposed to being processed via a slow-path using the protocol stack, wherein the processor determines that the TCP/IP packet can be processed via the fast-path, the TCP/IP packet being associated with one of the second plurality of CCBs, the processor causing said one of the second plurality of CCBs to be moved from the DRAM into the SRAM; and
a mechanism that moves the data portion of the TCP/IP packet from the network interface device and into a destination identified by the processing device, the data portion of the TCP/IP packet being written into the destination without the header portion of the TCP/IP packet being written into the destination and without the protocol stack doing substantial TCP protocol processing on the TCP/IP packet.
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17. A network interface device that is integrated with a processing device, the processing device executing a protocol stack, the network interface device comprising:
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an amount of SRAM, the SRAM storing a first plurality of communication control blocks (CCBs) that are under control of the network interface device;
an amount of DRAM, the DRAM storing a second plurality of CCBs that are under control of the network interface device;
means for analyzing a packet received onto the network interface device from a network and for generating from the packet a summary, the packet comprising a data portion and a header portion, the header portion including a TCP destination port value and a TCP source port value;
a processor that uses the summary and a content addressable memory to determine whether the packet can be processed via a fast-path by the network interface device as opposed to being processed via a slow-path using the protocol stack, wherein the packet is associated with one of the second plurality of CCBs, the processor causing said one of the second plurality of CCBs to be moved from the DRAM into the SRAM; and
a mechanism that moves the data portion of the packet from the network interface device and into a destination accessible by the processing device, the data portion of the packet being written into the destination without the header portion of the packet being written into the destination and without the protocol stack doing substantial TCP protocol processing on the packet.
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Specification