Interface architecture

• US 20020156975A1
• Filed: 01/29/2002
• Published: 10/24/2002
• Est. Priority Date: 01/29/2001
• Status: Active Grant

• Current Assignee: Braodband Storage LLC, Overland Storage Incorporated (Silicon Valley Technology Partners LLC)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Barry, David H., Godshalk, Ronald K. Jr., Lam, Danny, Olsen, Leonard D., Bolstad, Gregory D., Staub, John R., Priester, Wilbor George
• Granted Patent: US 6,745,286 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2048 where the redundant components share neither address space nor persistent storage
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 16/10 File systems; File servers
• CPC Class Codes: G06F 2201/84 Using snapshots, i.e. a logical point-in-time copy of the data
• CPC Class Codes: G06F 2211/1028 Distributed, i.e. distributed RAID systems with parity
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system

Abstract

A data interface architecture is described. The data interface architecture includes a network-side interface for communicating with a first bus and a storage-side interface for communicating with a second bus. The data interface architecture further includes a first data cache and a second data cache. The data interface architecture further includes a first parity engine, which is configured to perform parity operations for data transactions between the network-side interface and the first data cache, and a second parity engine, which is configured to perform parity operations for data transactions between the storage-side interface and the first data cache. The data interface architecture further includes a third parity engine, which is configured to perform parity operations for data transactions between the network-side interface and the second data cache, and a fourth parity engine, which is configured to perform parity operations for data transactions between the storage-side interface and the second data cache. The data interface architecture further includes control logic that is configured to manage the data transactions between the network-side interface and the first data cache, data transactions between the network-side interface and the second data cache, data transactions between the storage-side interface and the first data cache, and data transactions between the storage-side interface and the second data cache.

Claims

1. A data interface comprising:

a network-side interface for communicating with a first bus;

a storage-side interface for communicating with a second bus;

a first data cache;

a second data cache;

a first parity engine configured to perform parity operations for data transactions between said network-side interface and said first data cache;

a second parity engine configured to perform parity operations for data transactions between said storage-side interface and said first data cache;

a third parity engine configured to perform parity operations for data transactions between said network-side interface and said second data cache;

a fourth parity engine configured to perform parity operations for data transactions between said storage-side interface and said second data cache; and

control logic configured to manage said data transactions between said network-side interface and said first data cache, data transactions between said network-side interface and said second data cache, data transactions between said storage-side interface and said first data cache, and data transactions between said storage-side interface and said second data cache.

2. The data engine of claim 1, wherein said first bus comprises a PCI bus.

3. The data engine of claim 1, wherein said second bus comprises a PCI bus.

4. The data engine of claim 1, wherein said first bus comprises a PCI bus and said second bus comprises a PCI bus.

5. The data engine of claim 1, wherein said control logic interprets various bits in a PCI address as opcode bits.

6. The data engine of claim 1, wherein said control logic interprets various bits in a PCI address as parity index bits.

7. The data engine of claim 1, wherein said control logic interprets various bits in a PCI address as block size bits.

8. The data engine of claim 1, wherein said control logic interprets a first set of bits in a PCI address as opcode bits and a second set of bits in said PCI address as cache address bits.

9. A data interface comprising:

a means for communicating with a first bus;

a means for communicating with a second bus;

a first data cache;

a second data cache;

a first parity engine configured to perform parity operations for data transactions between said first data bus and said first data cache;

a second parity engine configured to perform parity operations for data transactions between said second data bus and said first data cache;

a third parity engine configured to perform parity operations for data transactions between said first data bus and said second data cache;

a fourth parity engine configured to perform parity operations for data transactions between said second data bus and said second data cache; and

control logic configured to manage said data transactions between said first data bus and said first data cache, data transactions between said first data bus and said second data cache, data transactions between said second data bus and said first data cache, and data transactions between said second data bus and said second data cache.