Memory device

• US 20020156988A1
• Filed: 03/20/2002
• Published: 10/24/2002
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Toyama, Masayuki, Sekibe, Tsutomu
• Granted Patent: US 6,938,144 B2
• Time in Patent Office: Days
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

In recent years, data volume to be handled have been increased, so that it has been required to increase the memory capacity without reducing portability and the like in a memory device provided with a non-volatile memory. In the present invention, a table for converting a logical address provided only in a conventional RAM to a physical address is provided in RAM and the non-volatile memory, thereby attempting to reduce the volume of RAM without lowering the memory capacity.

Claims

1. A memory device obtaining a physical address in a non-volatile memory from a logical address, comprising:

a primary allocation table obtaining a first physical address on the non-volatile memory corresponding to prescribed bits constituting said logical address; and

a secondary allocation table specified by said first physical address, and obtaining a second physical address on the non-volatile memory corresponding to bits different from said prescribed bits of said logical address.

2. The memory device according to claim 1, wherein said second physical address is information specifying a physical address of a representative write unit representing plural write units constituting a logical block which is a data block indicated by said logical address.

3. The memory device according to claim 2, comprising a writing means, in an operation configuring said logical block on said non-volatile memory, registering information for specifying a physical address of a representative write unit of said logical block on said secondary allocation table as said second physical address.

4. The memory device according to claim 1, comprising a writing means, in an operation configuring said logical block on said non-volatile memory, performing an operation invalidating a secondary allocation table specified by a first physical address corresponding to prescribed bits of a logical address indicating said logical block stored in prescribed write units, and performing an operation copying a secondary allocation table on which information for specifying a physical address of a representative write unit of said logical block is registered as said second physical address to other write units and writing information for specifying a physical address of said other write units into said primary allocation table as said first physical address.

5. The memory device according to claim 1, comprising a writing means, in an operation configuring said logical block on said non-volatile memory, performing an operation invalidating a secondary allocation table specified by a first physical address corresponding to a logical address indicating said logical block stored in prescribed physical blocks, each of which is an erase unit of data in said non-volatile memory, and performing an operation copying a secondary allocation table on which information for specifying a physical address of a representative write unit of said logical block is registered as said second physical address to a prescribed page of another physical block and writing information for specifying a physical address of said page into said primary allocation table as said first physical address.

6. The memory device according to claim 1, comprising a primary allocation table preparation means preparing said primary allocation table on the basis of an identification number held in said secondary allocation table and a physical address of said secondary allocation table.

7. The memory device according to claim 4, comprising a primary allocation table preparation means preparing a primary allocation table on the basis of a physical address of a secondary allocation table that has not been invalidated.

8. The memory device according to claim 5, comprising a primary allocation table preparation means preparing a primary allocation table on the basis of a physical address of a secondary allocation table that has not been authorized as invalid, which has been detected for the first time, of plural secondary allocation tables each having the same identification number indicating a region of a primary allocation table, within the same physical block.

9. The memory device according to claim 2, comprising a logical block table preparation means preparing a logical block table indicating a state of a logical block that includes a representative write unit whose physical address is specified by said second physical address on the basis of a flag indicating whether a secondary allocation table on which said second physical address has been registered is valid or invalid.

10. The memory device according to claim 1, comprising:

a physical block table indicating a state of a physical block, which is an erase unit of data in said non-volatile memory;

an address register indicating a physical block, which is an object for writing data;

an entry counter indicating a data volume written into a physical block indicated in said address register; and

a writing means configuring a new logical block on said non-volatile memory on the basis of said physical block table, said address register and said entry counter.

11. The memory device according to claim 10, wherein said writing means updates said physical block table, said address register, said entry counter and a logical block table indicating a state of a logical block on the basis of a state of said logical block newly configured.

12. The memory device according to claim 10, comprising an erase means erasing data of a prescribed physical block on the basis of contents indicated by said logical block table, said physical block table and said address register.

13. The memory device according to claim 10, comprising a physical block table preparation means determining whether or not data has been written into said physical block to prepare said physical block table on the basis of the determination.

14. The memory device according to claim 10, comprising:

a defective physical block determination means determining whether or not said physical block is defective; and

a use state setting means setting a use state of said physical block indicated by said physical block table to being during use when it is determined by said defective physical block determination means that said physical block is detective.

15. The memory device according to claim 10, comprising:

a defective physical block determination means determining whether or not said physical block is defective; and

a valid state setting means setting a state which a logical block table indicating a state of a logical block indicates for a logical block corresponding to said physical block determined as being defective by said defective physical block determination means, to a valid state.

16. The memory device according to any of claims 4, 5, 7 and 8, wherein a flag region storing a flag indicating whether a secondary allocation table is valid or invalid is provided in a write unit in which said secondary allocation table is stored.

18. The memory device according to claim 17, wherein said writing means writes said chain information into a management region of a write unit other than a write unit of which a prescribed management information is written into said management region.

19. The memory device according to claim 17, wherein said management information is a prescribed number or more of other chain information pieces.

20. The memory device according to claim 17, wherein said table includes:

a primary allocation table for acquiring a first physical address on a non-volatile memory corresponding to prescribed bits constituting said logical block; and

a secondary allocation table stored in a management region of a write unit specified by said first physical address and for acquiring a physical address of said representative write unit on the basis of bits other than said prescribed bits of said logical address, wherein

said management information is said secondary allocation table.

21. The memory device according to claim 17, comprising a read means reading a logical block on the basis of a physical address of said representative write unit and said chain information.

17. A memory device comprising:

a table for acquiring a physical address of a representative write unit representing a logical block of write units of a non-volatile memory, constituting said logical block, which is a data block indicated by a logical address, and including a data region into which data is stored and a management region in which management information for managing data is stored, from said logical address; and

a writing means writing chain information for acquiring a physical address of a write unit other than said representative write unit, constituting the same logical block as said representative write unit.

22. A memory device comprising:

a physical block table indicating a state of a physical block, which is an erase unit of data in a non-volatile memory;

an address register indicating a physical block, which is an object for writing data;

an entry counter indicating a data volume written into a physical block indicated in said address register; and

a writing means configuring a new logical block on said non-volatile memory on the basis of said physical block table, said address register and said entry counter.