Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs

• US 20020156998A1
• Filed: 09/07/2001
• Published: 10/24/2002
• Est. Priority Date: 07/29/1992
• Status: Abandoned Application

• Current Assignee: Tarofiss Data Limited Liability Company
• Original Assignee: Tarofiss Data Limited Liability Company
• Inventors: Casselman, Steven
• Application Number:
  US09/949,161
• Publication Number:
  US 20020156998A1
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Claims

1. A virtual network comprising:

plural distributed virtual computers interconnected over a communication network of individual links;

each distributed virtual computer comprising at least two respective ports each being connected over a respective link to another respective distributed virtual computer in the network;

each distributed virtual computer being connected to or resident within its own host computer;

each distributed virtual computer comprising reconfigurable FPGA logic elements, at least one of the FPGA elements being configured to have control capability over at least some of the remaining FPGA elements to react to instructions received from a host or from other nodes on the network to re-configure FPGA elements in the computation array to carry out a required task.