Inter-dice wafer level signal transfer methods for integrated circuits
First Claim
1. A method of transferring input or output (I/O) signals to a plurality of integrated circuit dice on one or more semiconductor substrates, the method comprising the steps of:
- forming inter-dice power supply conductive paths for connecting the power supply lines of nearby integrated circuit dice;
forming inter-dice ground conductive paths for connecting the ground lines of nearby integrated circuit dice;
forming one or more inter-dice signal conductive paths for connecting the I/O signals between nearby integrated circuit dice;
providing data transfer circuits for controlling the I/O procedures between nearby integrated circuit dice;
forming exposed conductive areas on said semiconductor substrates for connecting external I/O signals to the integrated circuits on said semiconductor substrates;
forming exposed conductive areas on said semiconductor substrates for connecting external power suppliers to the integrated circuits on said semiconductor substrates;
forming exposed conductive areas on said semiconductor substrates for connecting external ground lines to the integrated circuits on said semiconductor substrates;
wherein the I/O activities between external signals and said integrated circuit dice or the I/O activities between different integrated circuit dice are provided by a series of inter-dice data transfers between nearby dice.
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Abstract
The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically. The present application also makes it possible to build large area IC containing multiple dice. Extremely powerful products are realized using parallel processing capability of such multiple die integrated circuits.
48 Citations
53 Claims
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1. A method of transferring input or output (I/O) signals to a plurality of integrated circuit dice on one or more semiconductor substrates, the method comprising the steps of:
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forming inter-dice power supply conductive paths for connecting the power supply lines of nearby integrated circuit dice;
forming inter-dice ground conductive paths for connecting the ground lines of nearby integrated circuit dice;
forming one or more inter-dice signal conductive paths for connecting the I/O signals between nearby integrated circuit dice;
providing data transfer circuits for controlling the I/O procedures between nearby integrated circuit dice;
forming exposed conductive areas on said semiconductor substrates for connecting external I/O signals to the integrated circuits on said semiconductor substrates;
forming exposed conductive areas on said semiconductor substrates for connecting external power suppliers to the integrated circuits on said semiconductor substrates;
forming exposed conductive areas on said semiconductor substrates for connecting external ground lines to the integrated circuits on said semiconductor substrates;
wherein the I/O activities between external signals and said integrated circuit dice or the I/O activities between different integrated circuit dice are provided by a series of inter-dice data transfers between nearby dice. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 39)
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13. A semiconductor wafer comprising:
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a plurality of integrated circuit (IC) dice wherein each die includes a built-in self test circuit (BIST) for conducting a self test;
each die further includes a segmented seal ring surrounding said die having at least two segments separated by a narrow gap wherein each of said segments are in electric connection with an inter-dice bonding pad; and
an inter-dice connecting line interconnecting said segmented seal ring of a first IC die to a second IC die thus interconnecting said inter-dice bonding pad of said first IC die to said inter-dice bonding pad of said second IC die.
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18. A semiconductor wafer comprising:
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a plurality of integrated circuit (IC) dice;
an inter-dice power supply line connected between nearby dice;
an inter-dice ground line connected between nearby dice;
an inter-dice signal conductive line connected between nearby dice for transmitting signals between said nearby dice;
a data transfer control circuit for controlling a signal input and a signal output between said nearby dice interconnected with said inter-dice signal conductive line;
a first exposed conductive area for connecting to external input and output signal lines for transmitting I/O signals to said IC dice interconnected with said inter-dice signal conductive line;
a second exposed conductive area for connecting to an external power line for providing a high voltage to said IC dice interconnected with said inter-dice signal conductive line; and
a third exposed conductive area for connecting to an external ground line for providing a low voltage to said IC dice interconnected with said inter-dice signal conductive line.
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19. A semiconductor wafer comprising:
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a plurality of integrated circuit (IC) dice;
an inter-dice power supply line connected between nearby dice;
an inter-dice ground line connected between nearby dice; and
an inter-dice signal conductive line connected between nearby dice for transmitting signals between said nearby dice.
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36. A semiconductor wafer comprising a plurality of integrated circuit (IC) dice further comprising:
an inter-dice conductive line connected directly between nearby dice for transmitting signals between said nearby dice.
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38. A method of fabrication a semiconductor wafer having a plurality of integrated circuit (IC) dice comprising:
a) forming an inter-dice conductive line connected directly between nearby dice for transmitting signals between said nearby dice.
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40. A method of manufacturing a semiconductor wafer comprising:
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a) forming a plurality of integrated circuit (IC) dice on said wafer;
b) forming an inter-dice power supply line connected between nearby dice;
c) forming an inter-dice ground line connected between nearby dice; and
d) forming an inter-dice signal conductive line connected between nearby dice for transmitting signals between said nearby dice. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A method of testing a semiconductor wafer having a plurality of integrated circuit (IC) dice comprising:
a) forming an inter-dice conductive line connected directly between nearby dice for transmitting testing signals between said nearby dice. - View Dependent Claims (53)
Specification