Semiconductor structure and method for reducing charge damage

• US 20020158348A1
• Filed: 04/27/2001
• Published: 10/31/2002
• Est. Priority Date: 04/27/2001
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Charles, Alain, Petrucci, Joseph, Mautz, Karl, Maltabes, John
• Granted Patent: US 6,686,254 B2
• Time in Patent Office: Days
• US Class Current: 257/797
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure and a method for reducing charge damage during plasma etch processing are disclosed. Structures (22, 26, 28) for accumulating charge during plasma etch processing are provided on a semiconductor wafer (10), the structures (22, 26, 28) being electrically connected to device structures (30, 32).

Claims

1. A semiconductor structure for reducing charge damage during plasma etch processing, wherein structures for accumulating charge during plasma etch processing are provided on a semiconductor wafer, the structures being electrically connected to device structures.

2. A semiconductor structure according to claim 1, wherein the structures for accumulating charge are electric/parametric test structures.

3. A semiconductor structure according to claim 1, wherein the structures for accumulating charge are optical features.

4. A semiconductor structure according to claim 1, wherein the structures for accumulating charge are segmented into small features.

5. A semiconductor structure according to claim 1, wherein the structures for accumulating charge are located in the kerf area.

6. A semiconductor structure according to claim 1, wherein the structures for accumulating charge are connected to a grounded edge seal.

7. A semiconductor structure according to claim 1, wherein the structures for accumulating charge are connected to an active area on the semiconductor wafer.

8. A method for reducing charge damage during plasma etch processing, the method comprising the steps of

providing structures for accumulating charge on a semiconductor wafer,

connecting the structures electrically to device structures,

performing a plasma etch process, and

maintaining the connection during the plasma etch process.

9. A method according to claim 8, further comprising the step of selecting optical features as the structures for accumulating charge.

10. A method according to claim 8, further comprising the step of selecting electric/parametric test structures as the structures for accumulating charge.

11. A method according to claim 8, further comprising the steps of

segmenting the structures into small features, and

optimizing the spacing of the segmented structures,

thereby reducing the plasma etch rate of the features.

12. A method according to claim 8, further comprising the step of locating the structures in the kerf area.

13. A method according to claim 8, further comprising the step of connecting the structures to a grounded edge seal.

14. A method according to claim 8, further comprising the step of connecting the structures to an active area on the semiconductor wafer.

15. A method according to claim 8, further comprising the step of maintaining the structures for accumulating charge until the last stages of an overetch step.

16. A method according to claim 8, further comprising the step of maintaining the structures until higher power/dc bias etch steps are completed.