Semiconductor device

• US 20020158666A1
• Filed: 04/17/2002
• Published: 10/31/2002
• Est. Priority Date: 04/27/2001
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nagao, Shou, Tanada, Yoshifumi, Azami, Munehiro
• Granted Patent: US 6,975,142 B2
• Time in Patent Office: Days
• US Class Current: 326/83
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H03K 19/01714 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node a into a floating state. When the node α is in the floating state, a potential of the node a is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Claims

1. A semiconductor device comprising:

a first transistor having a first impurity region connected to a first power source;

a second transistor having a first impurity region connected to a second power source;

a third transistor having a first impurity region connected to the first power source; and

a fourth transistor having a first impurity region connected to the second power source, wherein;

the first to fourth transistors have a same conductivity type;

a second impurity region of the first transistor and a second impurity region of the second transistor are connected to one terminal of a capacitance;

a second impurity region of the third transistor, a second impurity region of the fourth transistor, and a gate electrode of the first transistor are connected to the other terminal of the capacitance;

a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to an input signal line; and

a gate electrode of the third transistor is connected to the first power source.

4. A semiconductor device according to claim 1, wherein the capacitance uses a capacitance between the gate electrode of the first transistor and one of the impurity regions.

6. A semiconductor device according to claim 1, wherein the capacitance is a capacitance constituted by using any two materials of an active layer material, a material forming the gate electrodes, and a wiring material.

8. A semiconductor device according to claim 1, wherein the one conductivity is an N-channel type.

10. A semiconductor device according to claim 1, wherein the one conductivity is a P-channel type.

12. A semiconductor device according to claim 1, wherein:

the one conductivity is an N-channel type;

a potential at a time when the input signal is at an H level is equal to a third power source potential, and a potential at a time when the input signal is at an L level is equal to a fourth power source potential; and

a relation of a second power source potential the fourth power source potential<

the third power source potential a first power source potential is satisfied.

14. A semiconductor device according to claim 1, wherein:

the one conductivity is a P-channel type;

a potential at a time when the input signal is at a H level is equal to a third power source potential, and a potential at a time when the input signal is at a L level is equal to a fourth power source potential; and

a relation of a first power source potential the fourth power source potential<

the third power source potential a second power source potential is satisfied.

16. A semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of an inverter, a buffer, and a level shifter.

18. A semiconductor device according to claim 1, wherein the semiconductor device is applied to an electronic equipment selected from the group consisting of a liquid crystal display, a video camera, a notebook personal computer, a portable information terminal, an on-vehicle audio apparatus, a digital camera and a portable telephone.

2. A semiconductor device comprising:

a first transistor having a first impurity region connected to a first power source;

a second transistor having a first impurity region connected to a second power source;

a third transistor having a first impurity region connected to the first power source;

a fourth transistor having a first impurity region connected to the second power source, wherein;

the first to fourth transistors have a same conductivity type;

a second impurity region of the first transistor and a second impurity region of the a second transistor are connected to one terminal of a capacitance;

a second impurity region of the third transistor, a second impurity region of the fourth transistor, and a gate electrode of the first transistor are connected to the other terminal of the capacitance;

a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to a first input signal line; and

a gate electrode of the third transistor is connected to a second input signal line.

3. A semiconductor device according to claim 2, wherein the second input signal line is the signal line to which an inversion signal of a signal inputted to the first input signal line is inputted.

5. A semiconductor device according to claim 2, wherein the capacitance uses a capacitance between the gate electrode of the first transistor and one of the impurity regions.

7. A semiconductor device according to claim 2, wherein the capacitance is a capacitance constituted by using any two materials of an active layer material, a material forming the gate electrodes, and a wiring material.

9. A semiconductor device according to claim 2, wherein the one conductivity is an N-channel type.

11. A semiconductor device according to claim 2, wherein the one conductivity is a P-channel type.

13. A semiconductor device according to claim 2, wherein:

the one conductivity is an N-channel type;

a potential at a time when the input signal is at an H level is equal to a third power source potential, and a potential at a time when the input signal is at an L level is equal to a fourth power source potential; and

a relation of a second power source potential the fourth power source potential<

the third power source potential a first power source potential is satisfied.

15. A semiconductor device according to claim 2, wherein:

the one conductivity is a P-channel type;

a potential at a time when the input signal is at a H level is equal to a third power source potential, and a potential at a time when the input signal is at a L level is equal to a fourth power source potential; and

a relation of a first power source potential the fourth power source potential<

the third power source potential a second power source potential is satisfied.

17. A semiconductor device according to claim 2, wherein the semiconductor device is one selected from the group consisting of an inverter, a buffer, and a level shifter.

19. A semiconductor device according to claim 2, wherein the semiconductor device is applied to an electronic equipment selected from the group consisting of a liquid crystal display, a video camera, a notebook personal computer, a portable information terminal, an on-vehicle audio apparatus, a digital camera and a portable telephone.

20. A display device having at least one driving circuit, the driving circuit comprising:

a first transistor having a first impurity region connected to a first power source;

a second transistor having a first impurity region connected to a second power source;

a third transistor having a first impurity region connected to the first power source; and

a fourth transistor having a first impurity region connected to the second power source, wherein;

the first to fourth transistors have a same conductivity type;

a second impurity region of the first transistor and a second impurity region of the second transistor are connected to one terminal of a capacitance;

a second impurity region of the third transistor, a second impurity region of the fourth transistor, and a gate electrode of the first transistor are connected to the other terminal of the capacitance;

a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to an input signal line; and

a gate electrode of the third transistor is connected to the first power source.

21. A display device having at least one driving circuit, the driving circuit comprising:

a first transistor having a first impurity region connected to a first power source;

a second transistor having a first impurity region connected to a second power source;

a third transistor having a first impurity region connected to the first power source;

a fourth transistor having a first impurity region connected to the second power source, wherein;

the first to fourth transistors have a same conductivity type;

a second impurity region of the first transistor and a second impurity region of the second transistor are connected to one terminal of a capacitance;

a second impurity region of the third transistor, a second impurity region of the fourth transistor, and a gate electrode of the first transistor are connected to the other terminal of the capacitance;

a gate electrode of the second transistor and a gate electrode of the fourth transistor are connected to a first input signal line; and

a gate electrode of the third transistor is connected to a second input signal line.