CAM circuit with radiation resistance
First Claim
1. A content addressable memory (CAM) circuit comprising:
- a random access memory (RAM) array including a first memory cell;
a CAM array including a CAM cell, wherein the CAM cell includes a second memory cell; and
a control circuit connected to the RAM array and the CAM array for systematically refreshing the CAM array by reading a data value from the first memory cell, and then writing the data value to the second memory cell.
11 Assignments
0 Petitions
Accused Products
Abstract
A CAM circuit including a RAM array, a CAM array, and a control circuit that systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually restoring data that has been corrupted by radiation. The RAM and CAM arrays can be formed on the same substrate, but are preferably fabricated on separate substrates and mounted in a single package or on a PCB. Both the CAM and RAM can be formed using any conventional memory type (e.g., SRAM, DRAM, NVRAM), and the CAM array can be a binary, ternary, or quad CAM array. The CAM and RAM arrays can be formed on different substrates, or the same substrate. A system including an SRAM ternary CAM array and a RAM array perform quad CAM functions by performing read functions utilizing only the RAM array, while performing lookup functions using the ternary CAM array.
9 Citations
22 Claims
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1. A content addressable memory (CAM) circuit comprising:
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a random access memory (RAM) array including a first memory cell;
a CAM array including a CAM cell, wherein the CAM cell includes a second memory cell; and
a control circuit connected to the RAM array and the CAM array for systematically refreshing the CAM array by reading a data value from the first memory cell, and then writing the data value to the second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A content addressable memory (CAM) circuit comprising:
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a random access memory (RAM) array including a first memory cell;
a CAM array including a CAM cell, wherein the CAM cell includes a second memory cell; and
means for systematically refreshing the CAM array by reading a data value from the first memory cell, and then writing the data value to the second memory cell.
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22. A method for operating a content addressable memory (CAM) circuit including a random access memory (RAM) array having a first memory cell, and a CAM array having a second memory cell, the method comprising:
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writing a data value to the first memory cell of the RAM array and to the second memory cell of the CAM array; and
systematically refreshing the CAM array by reading the data value from the first memory cell, and then writing the data value to the second memory cell.
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Specification