Memory circuit and coherent detection circuit
First Claim
1. A memory circuit for temporarily storing information symbols to receive a signal according to a CDMA system which allows multi-code communication and carry out coherent detection using a pilot symbol, comprising:
- a plurality of electrically independent memory blocks, each memory block corresponding to each code in said multi-code communication; and
a memory interface section that carries out data write and data read on each of said plurality of blocks periodically while controlling access timing so that write access and read access to one memory block do not occur simultaneously.
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Accused Products
Abstract
The memory circuit of the present invention temporarily stores information symbols included in a reception signal according to a CDMA system which allows multi-code communication to carry out coherent detection using a pilot symbol. The memory circuit of the present invention is constructed of a plurality of electrically independent memory blocks. Each memory block corresponds to one code and one slot of an information symbol. Write access and read access to memory blocks are generated periodically on condition that write access and read access to one memory block do not occur simultaneously. Blocks to which no access is generated are forcibly set to a low power consumption mode to reduce power consumption caused by accesses.
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Citations
12 Claims
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1. A memory circuit for temporarily storing information symbols to receive a signal according to a CDMA system which allows multi-code communication and carry out coherent detection using a pilot symbol, comprising:
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a plurality of electrically independent memory blocks, each memory block corresponding to each code in said multi-code communication; and
a memory interface section that carries out data write and data read on each of said plurality of blocks periodically while controlling access timing so that write access and read access to one memory block do not occur simultaneously.
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2. A memory circuit for temporarily storing a predetermined number of information symbols to receive a signal according to a CDMA system which allows multi-code communication and carry out coherent detection using a pilot symbol, comprising:
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a plurality of electrically independent memory blocks, each memory block corresponding to one code in said multi-code communication and one slot of the reception signal; and
a memory interface section that carries out data write and data read on each of said plurality of blocks periodically while controlling access timing so that write access and read access to one memory block do not occur simultaneously. - View Dependent Claims (3)
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4. A memory circuit for temporarily storing a predetermined number of information symbols to receive a signal according to a CDMA system which allows multi-code communication and carry out coherent detection using a pilot symbol, comprising:
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a plurality of electrically independent memory blocks, each memory block corresponding to one code in said multi-code communication and one slot of the reception signal;
a memory interface section that carries out data write and data read on each of said plurality of blocks periodically while controlling access timing so that write access and read access to one memory block do not occur simultaneously; and
a memory operation control section that sets memory blocks to which no access is generated to a low power consumption mode. - View Dependent Claims (5)
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6. A coherent detection circuit using a pilot symbol that carries out coherent detection by estimating phase variations using known pilot symbols periodically inserted in information symbols and compensating for the phases of information symbols, comprising:
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an information symbol storage memory circuit having a plurality of electrically independent memory blocks, each memory block corresponding to one code and one slot of the reception signal in said multi-code communication; and
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a phase estimation section that carries out phase estimations of pilot symbols using a plurality of pilot symbols located near a slot to be detected;
an interpolation section that determines the phases of information symbols based on the estimation result of said phase estimation section;
a coherent detection section that carries out coherent detection at timing that matches the phases of said information symbols corrected by said interpolation section; and
a memory operation control section that controls the respective operating modes of said plurality of memory blocks of said information symbol storage memory based on multi-code information and slot information and sets memory blocks to which no access is generated to a low power consumption mode. - View Dependent Claims (7, 8, 9)
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10. An information symbol storage memory access control method, comprising the steps of:
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providing an information symbol storage memory whose memory area is divided into a plurality of electrically independent memory blocks based on at least one of information on the number of multi-codes and slot information; and
carrying out data write and data read on each of said plurality of blocks periodically while controlling access timing so that write access and read access to one memory block do not occur simultaneously.
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11. An information symbol storage memory access control method, comprising the steps of:
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providing an information symbol storage memory whose memory area is divided into a plurality of electrically independent memory blocks based on at least one of information on the number of multi-codes and slot information;
carrying out data write and data read on each of said plurality of blocks periodically while controlling access timing so that write access and read access to one memory block do not occur simultaneously; and
setting said blocks that are subject to neither data write nor data read to a low power consumption mode. - View Dependent Claims (12)
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Specification