Computational circuits and methods for signal deconstruction/reconstruction in wireless transceivers

• US 20020159532A1
• Filed: 07/30/2001
• Published: 10/31/2002
• Est. Priority Date: 03/23/2001
• Status: Abandoned Application

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Seven Generations Energy Ltd.
• Inventors: Wight, James Stuart
• Application Number:
  US09/918,106
• Publication Number:
  US 20020159532A1
• Time in Patent Office: Days
• US Class Current: 375/260
• CPC Class Codes: H03C 3/40 using two signal paths the outputs of which have a predetermined phase difference and at least one output being amplitude-modulated
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 2215/067 by modulation dispersion
• CPC Class Codes: H04L 27/2614 Peak power aspects

Abstract

Circuits and methods are provided for use in an RF transmitter to complement the digital generation of a non-constant envelope modulation signals therein. A digital signal processor is configured for deconstructing a resultant signal having an undesirable property into one or more deconstruct signals which do not have the undesirable property. In a preferred embodiment the resultant signal is preconditioned by applying a preconditioning deconstruction process to an earlier signal from which said resultant is derived for deconstructing the earlier signal into one or more preconditioned deconstruct signals having an improved property over the earlier signal. For OFDM modulation scheme this undesirable property is a relatively high peak-to-average power ratio. Signals derived from the deconstruct signals are subject to conversion to analog signals and processing by power efficient, dynarnic-range limited analog circuits i.e. S Class power amplifiers and low compression-point up-converters, before being recombined for transmission.

Claims

1. A signal deconstruction circuit for use in an RF transmitter and configured for complementing modulation circuitry of said transmitter for digitally generating a non-constant envelope modulation signal, said deconstruction circuit comprising a digital signal processor configured for deconstructing a resultant signal having an undesirable property into one or more deconstruct signals which do not have said undesirable property, whereby signals derived from said deconstruct signals are subject to conversion to analog signals, processing by power efficient, dynamic-range limited analog circuits and recombination.

2. A circuit according to claim 1 wherein said undesirable property is a relatively high peak-to-average power ratio.

3. A circuit according to claim 2 wherein said modulation circuitry comprises an Inverse Fourier transform processor and said deconstruction circuit is operative on said resultant signal after said Inverse Fourier transform processor.

20. A circuit according to claim 3 comprising a virtual range-hopped engine configured for shifting a peak signal output from said Inverse Fourier transform processor to time samples targeted for attenuation by a preselected windowing function.

4. A signal deconstruction circuit for use in an RF transmitter and configured for complementing modulation circuitry of said transmitter for digitally generating a non-constant envelope modulation signal, said deconstruction circuit comprising a digital signal processor configured for deconstructing a resultant signal having an undesirable property into a plurality of deconstruct signals which do not have said undesirable property.

5. A circuit according to claim 4 wherein said undesirable property is a relatively high peak-to-average power ratio.

6. A circuit according to claim 5 wherein said modulation circuitry comprises an Inverse Fourier transform processor and said deconstruction circuit is operative on said resultant signal prior to said Inverse Fourier transform processor.

7. A circuit according to claim 5 wherein said modulation circuitry comprises an Inverse Fourier processor and said deconstruction circuit is operative on said resultant signal after said Inverse Fourier transform processor.

8. A circuit according to claim 6 comprising a carrier-sorting engine and said modulation is OFDM.

9. A circuit according to claim 8 wherein said carrier-sorting engine sorts carriers of said resultant signal into a plurality of groups, each said group forming one said deconstruct signal whereby said modulation circuitry comprises a plurality of Inverse Fourier transform processors for transforming said deconstruct signals, each said Inverse Fourier transform processor being smaller than would be required to transform said resultant signal without said deconstruction of the same into said deconstruct signals.

10. A circuit according to claim 9 wherein said carriers are simultaneously sorted in more than one way to produce a plurality of alternative deconstruct signals for each said group, whereby said deconstruct signals are selected from one said group on the basis of having the best peak-to-average power ratio.

11. A circuit according to claim 7 comprising a phasor fragmentation engine.

12. A circuit according to claim 11 wherein said phasor fragmentation engine deconstructs said resultant signal into a plurality of equal, varying amplitude deconstruct signals the phasors of which combine to form a phasor corresponding to said resultant signal, wherein said amplitude of said deconstruct signals is a predetermined proportion of the variation of the amplitude of said resultant signal about the mean amplitude thereof.

13. A circuit according to claim 12 wherein said phasor fragmentation engine deconstructs said resultant signal into two equal, varying amplitude deconstruct signals, said deconstructing comprising converting sequences of complex time samples output from said Inverse Fourier transform processor into two parallel sequences of equal magnitude phasor at two phases whereby said phases are calculated to be θ

−

φ and

θ

+φ

, respectively, whereby φ

=cos<sup>−

1</sup>(0.5V/V_PHASOR) wherein V is the amplitude of the current sample of said resultant signal and V_PHASOR is the amplitude of said deconstruct signals calculated to be K₁V-K₂ wherein K₁ and K₂ are constants.

14. A circuit according to claim 11 wherein said phasor fragmentation engine deconstructs said resultant signal into a plurality of equal and constant amplitude deconstruct signals.

15. A circuit according to claim 14 wherein said resultant signal is preconditioned by a second deconstruction circuit.

16. A circuit according to claim 15 wherein said second deconstruction circuit comprises a carrier sorting engine.

17. A circuit according to claim 15 wherein said second deconstruction circuit comprises a preconditioning phasor fragmentation engine for preconditioning a second resultant signal prior to said processing of said resultant signal, wherein said preconditioning phasor fragmentation engine deconstructs said second resultant signal into a plurality of equal but varying amplitude preconditioned deconstruct signals the phasors of which combine to form a phasor corresponding to said second resultant signal, wherein said amplitude of said preconditioned deconstruct signals is a predetermined proportion of the variation of the amplitude of said second resultant signal about the mean amplitude thereof.

18. A circuit according to claim 15 wherein said phasor fragmentation engine is configured for converting sequences of complex time samples output from said Inverse Fourier transform processor into two parallel sequences of two equal magnitude phasors, equal to Vmax/2, at two phases, whereby said phases of said two equal magnitude phasors are calculated to be θ

−

φ and

θ

+φ

, respectively, whereby φ

=cos<sup>−

1</sup>(V/Vmax) wherein V is the amplitude of the current sample of said resultant signal and Vmax is the maximum amplitude of said resultant signal over the period of said sequence.

19. A circuit according to claim 14 wherein said phasor fragmentation engine is configured for converting sequences of complex time samples output from said Inverse Fourier transform processor into three parallel sequences of three equal magnitude phasors, equal to Vmax/3, at three phases, whereby said phases of two said equal magnitude phasors are calculated to be θ

−

φ and

θ

+φ

, respectively, and said third phase is equal to the phase of said resultant signal, whereby φ

=cos<sup>−

1</sup>[(1.5 V_MAX)−

0.5], V being the amplitude of the current sample of said resultant signal and Vmax being the maximum amplitude of said resultant signal over the period of said sequence.

21. A circuit according to claim 15 wherein said second deconstruction circuit comprises a light windowing engine.

22. A circuit according to claim 15 further comprising an amplitude and phase comparison calibration circuit for adjusting differences in channel gains and phases between said deconstruct signals when combined following parallel up-converter/power amplifier chains to regenerate a modulated waveform, said calibration circuit comprising an error signal generator for generating error signals configured for adjusting said regenerated waveform.

23. A circuit according to claim 19 wherein said modulation is OFDM.

24. A circuit according to claim 23 further comprising an amplitude and phase comparison calibration circuit for adjusting differences in channel gains and phases between said deconstruct signals when combined following parallel up-converter/power amplifier chains to regenerate a modulated waveform, said calibration circuit comprising an error signal generator for generating error signals configured for adjusting said regenerated waveform.

26. A method according to claim 25 whereby said undesirable property is a relatively high peak-to-average power ratio.

27. A method according to claim 26 whereby said modulation signal is generated using an Inverse Fourier transform processor and said deconstructing is performed prior to modulation by said Inverse Fourier transform processor.

28. A method according to claim 26 whereby said modulation signal is generated using an Inverse Fourier transform processor and said deconstructing is performed subsequent to modulation by said Inverse Fourier transform processor.

29. A method according to claim 27 whereby said deconstructing comprises sorting carriers of said resultant signal into a plurality of groups, each said group forming one said deconstruct signal, whereby said modulation is performed by a plurality of Inverse Fourier transform processors for transforming said deconstruct signals, each said Inverse Fourier transform processor being smaller than would be required to transform said resultant signal without said deconstructing step.

30. A method according to claim 29 whereby said carriers are simultaneously sorted in more than one way to produce a plurality of alternative deconstruct signals for each said group and selecting said deconstruct signals for one said group on the basis of having the best peak-to-average power ratio.

31. A method according to claim 28 whereby said resultant signal is deconstructed into a plurality of equal, varying amplitude deconstruct signals the phasors of which combine to form a phasor corresponding to said resultant signal, wherein said amplitude of said deconstruct signals is a predetermined proportion of the variation of the amplitude of said resultant signal about the mean amplitude thereof.

32. A method according to claim 31 wherein said resultant signal is deconstructed into two equal, varying amplitude deconstruct signals and said deconstructing comprising converting sequences of complex time samples output from said Inverse Fourier transform processor into two parallel sequences of equal magnitude phasors, equal to Vmax/2, at two phases whereby said phases are calculated to be θ

−

φ and

θ

+φ

, respectively, whereby θ

=cos<sup>−

1</sup>(0.5V/V_PHASOR) wherein V is the amplitude of the current sample of said resultant signal and V_PHASOR is the amplitude of said deconstruct signals calculated to be K₁V−

K₂ wherein K₁ and K₂ are constants.

33. A method according to claim 28 whereby said resultant signal is deconstructed into a plurality of equal and constant amplitude deconstruct signals.

34. A method according to claim 33 whereby said resultant signal is deconstructed into two said deconstruct signals and said resultant signal is preconditioned by deconstructing a second resultant signal into a plurality of equal but varying amplitude preconditioned deconstruct signals the phasors of which combine to form a phasor corresponding to said second resultant signal, wherein said amplitude of said preconditioned deconstruct signals is a predetermined proportion of the variation of the amplitude of said second resultant signal about the mean amplitude thereof.

35. A method according to claim 33 comprising converting sequences of complex time samples output from said Inverse Fourier transform processor into three parallel sequences of three equal magnitude phasors, equal to Vmax/3, at three phases, whereby said phases of two said equal magnitude phasors are calculated to be θ

−

φ and

θ

+φ

, respectively, and said third phase is equal to the phase of said resultant signal, whereby φ

=cos<sup>−

1</sup>[(1.5V/V_MAX)−

0.5], V being the amplitude of the current sample of said resultant signal and Vmax being the maximum amplitude of said resultant signal over the period of said sequence.

36. A method according to claim 28 comprising shifting a peak signal output from said Inverse Fourier transform processor to time samples targeted for attenuation by a preselected windowing function.

25. A signal deconstruction method for complementing the generation of a digitally generated non-constant envelope modulation signal in an RF transmitter, said method comprising deconstructing a resultant signal having an undesirable property into a plurality of deconstruct signals which do not have said undesirable property whereby signals derived from said deconstruct signals are subject to conversion to analog signals, processing by power efficient, dynamic-range limited analog circuits and recombination.