Trench-gate semiconductor devices and their manufacture

• US 20020160573A1
• Filed: 04/26/2002
• Published: 10/31/2002
• Est. Priority Date: 04/28/2001
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Grover, Raymond J., Peake, Steven T., Petkos, Georgios, Forbes, Peter J., Farr, Robert J., Rogers, Christopher M.
• Granted Patent: US 6,534,367 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66848 with a Schottky gate, i.e. MESFET
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11). Furthermore, implantation of the source region (13) is facilitated, and a channel-accommodating region (15) can also be provided using a high energy implant (61) after providing the insulating overlayer (18).

Claims

1. A method of manufacturing a trench-gate semiconductor device having a trench-gate in a trench that extends from a source region through a channel-accommodating region to a drain region, wherein:

(a) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window in a first mask at a surface of a semiconductor body,

(b) a trench is etched into the body at the narrow window, and the gate is provided in the trench,

(c) the source region is provided so as to be adjacent to a sidewall of the trench, and

(d) an insulating overlayer is provided over the trench-gate using the following sequence of steps;

removing the sidewall extensions to leave at least a part of the first mask with the wider window at the surface of the body,

depositing insulating material to a thickness that is sufficient to fill the wider window and to extend above the wider window and on the first mask part,

etching back the insulating material to leave the insulating overlayer in the wider window in the first mask part,

and then removing the first mask part before providing a source electrode to contact the source region and an adjacent surface region of the body and to extend over the insulating overlayer over the trench-gate.

2. A method according to claim 1, wherein the sequence of stages (b) and (c) are such that the source region defined in stage (c) has a doping concentration of a first conductivity type that is provided in the body after providing the gate in the trench in stage (b).

3. A method according to claim 1 or claim 2, wherein the source region is provided in stage (c) in such a way as to be self-aligned with the trench-gate by means of the sidewall extensions.

4. A method according to claim 3, wherein the source region is provided after the gate, using the following sequence of steps before depositing the insulating material for the insulating overlayer:

removing the sidewall extensions to leave at least a part of the first mask with the wider window at the surface of the body and to form within the wider window a doping window between the first mask part and the trench-gate, and

introducing dopant of a first conductivity type into the body via the wider window so as to form the source region adjacent to the trench-gate and extending laterally slightly below the first mask part.

5. A method according to any one of the preceding claims, wherein the trench is etched in stage (b) through a silicon body portion that has a doping concentration of the first conductivity type that extends from the surface into an underlying area to provide a part of the drain region, and wherein a gate dielectric layer is formed by thermal oxidation of the silicon body portion at the walls of the trench.

6. A method according to any one of the preceding claims, wherein a channel-accommodating region of a second conductivity type is formed adjacent to the trench-gate using the following sequence of steps:

removing the first mask part in stage (d) to form a doping window in the insulating overlayer, and

introducing dopant of the second conductivity type into the body via this doping window so as to form the channel-accommodating region at the doping window and extending laterally below the insulating overlayer to the trench.

7. A method according to claim 6, wherein the channel-accommodating region is formed by ion implantation of the dopant of the second conductivity type after stage (d), at a sufficiently high energy and in a sufficiently high dose that the dopant ions implanted at the doping window in the insulating overlayer are scattered laterally below the insulating overlayer to reach the trench.

8. A method according to claim 7, wherein the dopant ions are of boron having an implantation energy in excess of 200 keV.

9. A method according to any one of the preceding claims, wherein the gate is provided in a part of the trench below the level of the surface of the body, and the subsequently deposited and etched-back insulating material of stage (d) is left in the upper part of the trench and extends laterally from the trench into the wider window of the first mask part.

10. A method according to any one of the preceding claims, wherein the first mask in stage (a) is a composite comprising an upper layer part on a lower layer part, the upper layer part is of a different material to the lower layer part so as to etchable from the lower layer part, and the upper layer part is etched away from the lower layer part before providing the insulating overlayer in stage (d).

11. A method according to claim 10, wherein the upper layer part is of silicon dioxide, and the lower layer part is of silicon nitride.

12. A method according to any one of the preceding claims, wherein, after providing the insulating overlayer in stage (d), the channel-accommodating region is contacted using the following sequence of steps:

removing the first mask part to form a contact window in the insulating overlayer,

introducing dopant of the second conductivity type into the body via the contact window so as to form a more highly doped contact region for the channel-accommodating region, and

depositing the source electrode to contact the source region and the contact region at the contact window and to extend over the insulating overlayer over the trench-gate.

13. A method according to any one of the preceding claims, wherein, after removing the first mask part in stage (d) and before providing the source electrode, the insulating material of the insulating overlayer is isotropically etched back a sufficient distance to increase the area of the source region not covered by the insulating overlayer.

14. A method according to any one of the preceding claims, wherein the gate is provided in the trench before removing the sidewall extensions to re-expose the wider window.

15. A method according to any one of the preceding claims, wherein, after etching the trench, the sidewall extensions are removed to re-expose the wider window, and then gate material is deposited to fill the wider window and the trench therein and is etched back to be left as the gate in the trench.

16. A method according to claim 15, wherein, before removing the sidewall extensions, insulating material is deposited to a sufficient thickness to fill the trench and to extend above the trench and over the sidewall extensions and on the first mask, and the sidewall extensions are then removed in an etching step that etches back this insulating material until it is left in only a lower part of the trench, after which the gate is provided in a part of the trench above this insulating material in the lower part.

17. A method according to any one of the preceding claims, wherein the first mask comprises silicon nitride, the sidewall extensions comprise silicon dioxide, and the insulating overlayer comprises silicon dioxide.

18. A method according to any one of claims 1 to 16, wherein the sidewall extensions comprise polysilicon material on a thin insulating layer, and the polysilicon material of the sidewall extensions is removed in the etching stage (b) that provides the trench.