Memory control device and LSI
First Claim
1. A memory control device for arbitrating memory access contention among a plurality of bus masters sharing a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, the memory control device comprising:
- holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate information indicating (i) a transfer rate at which a corresponding bus master performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;
reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;
bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a bus master takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding bus master is capable of transferring at a corresponding transfer rate within the reference time period; and
use right granting means for granting the bus use right to each bus master for a corresponding bus use permission time period within each reference time period that repeats cyclically.
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Accused Products
Abstract
A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.
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Citations
19 Claims
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1. A memory control device for arbitrating memory access contention among a plurality of bus masters sharing a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, the memory control device comprising:
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holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate information indicating (i) a transfer rate at which a corresponding bus master performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;
reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;
bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a bus master takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding bus master is capable of transferring at a corresponding transfer rate within the reference time period; and
use right granting means for granting the bus use right to each bus master for a corresponding bus use permission time period within each reference time period that repeats cyclically. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory control device for arbitrating memory access contention among a plurality of bus masters accessing separate memory areas within a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, the memory control device comprising:
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holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate information indicating (i) a transfer rate at which a corresponding bus master performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;
reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;
bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a bus master takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding bus master is capable of transferring at a corresponding transfer rate within the reference time period; and
use right granting means for granting the bus use right to each bus master for a corresponding bus use permission time period within each reference time period that repeats cyclically. - View Dependent Claims (11, 12, 13, 15, 16, 17, 18, 19)
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14. An LSI including (i) a plurality of circuits that share a memory and (ii) a memory control device for arbitrating memory access contention by selectively granting a bus use right that permits the usage a memory bus to one of the plurality of circuits at a time, each circuit is required to perform data transfer to or from the memory at a fixed transfer rate, the memory control device comprising:
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holding means for holding transfer rate information regarding each of the plurality of the circuits, the transfer rate information indicating (i) a transfer rate at which a corresponding circuit performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;
reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;
bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a circuit takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding circuit is capable of transferring at a corresponding transfer rate within the reference time period; and
use right granting means for granting the bus use right to each circuit for a corresponding bus use permission time period within each reference time period that repeats cyclically.
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Specification