Data processing circuits and interfaces
First Claim
1. A processor embedded with other circuitry as part of an application specific integrated circuit, the processor comprising:
- control means for controlling operations within the processor in accordance with a stored program, the program comprising stored instructions selected from a predetermined instruction set;
a plurality of registers for storing calculated values;
addressing means operable under control of the stored instructions to perform addressing operations addressing a data storage space of the processor, at least one said registers being operable as an address register as part of the addressing means for storing calculated address values for use in said addressing operations;
a common arithmetic unit having input and output data paths each of width n bits, and being operable under control of the stored instructions both to calculate general data values in co-operation with the registers, and to calculate address values in co-operation with said address register;
wherein at least one of said registers is operable as a wide data register of width substantially greater than n bits for storing results of arithmetic operations wider than n bits; and
a shifting circuit of said greater width is interposed between the output path of the arithmetic unit and the wide data register, with a feedback path also of said greater width from data outputs of the wide data register, and is operable under control of the stored instructions to generate a shifted result of said greater width in the wide data register in response to at least a multiplication, division or normalisation instruction, by repeated operation of the arithmetic unit in cooperation with the shifting circuit and the wide data register.
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Accused Products
Abstract
An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.
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Citations
26 Claims
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1. A processor embedded with other circuitry as part of an application specific integrated circuit, the processor comprising:
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control means for controlling operations within the processor in accordance with a stored program, the program comprising stored instructions selected from a predetermined instruction set;
a plurality of registers for storing calculated values;
addressing means operable under control of the stored instructions to perform addressing operations addressing a data storage space of the processor, at least one said registers being operable as an address register as part of the addressing means for storing calculated address values for use in said addressing operations;
a common arithmetic unit having input and output data paths each of width n bits, and being operable under control of the stored instructions both to calculate general data values in co-operation with the registers, and to calculate address values in co-operation with said address register;
wherein at least one of said registers is operable as a wide data register of width substantially greater than n bits for storing results of arithmetic operations wider than n bits; and
a shifting circuit of said greater width is interposed between the output path of the arithmetic unit and the wide data register, with a feedback path also of said greater width from data outputs of the wide data register, and is operable under control of the stored instructions to generate a shifted result of said greater width in the wide data register in response to at least a multiplication, division or normalisation instruction, by repeated operation of the arithmetic unit in cooperation with the shifting circuit and the wide data register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification