Hierarchical access of test access ports in embedded core integrated circuits

• US 20020162063A1
• Filed: 06/14/2002
• Published: 10/31/2002
• Est. Priority Date: 02/18/1998
• Status: Active Grant

• Current Assignee: Lee D. Whetsel
• Original Assignee: Lee D. Whetsel
• Inventors: Whetsel, Lee D.
• Granted Patent: US 6,975,980 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318561 Identification of the subpart
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE Standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Claims

1. An integrated circuit comprising:

A. plural embedded cores formed in the integrated circuit;

B. a test access port associated with and connected to each core;

C. one IC test access port on the integrated circuit, including one test data input lead, one test data output lead, one test clock lead and one test mode select lead;

D. a linking module connected between the one IC test access port and the core test access ports;

E. a select output lead from one of the cores that passes through the linking module as an external core output;

F. an external core enable lead that connects to the linking module;

G. a gate in the linking module receiving the external core enable lead and producing an enable signal to the one core;

2. The integrated circuit of claim 1 in which the test data input lead connects to the linking module and each of the core test access ports.

3. The integrated circuit of claim 1 in which the test clock and test mode select lead connect to the linking module and each core test access port.

4. The integrated circuit of claim 1 including an enable and select lead connected between the linking module and each core access port.

5. The integrated circuit of claim 1 including a first multiplexer selecting a connection between the linking module and the test data output lead and the test data output leads from each core test access port and the test data output lead, and a second multiplexer selecting between the test data output leads from each core test access port.

6. The integrated circuit of claim 1 in which the linking module includes:

i. a control module connected to the clock and mode select leads of the IC test access port, and having plural outputs;

ii. a shift register connected to at least two of the control module outputs and serially connected to the test data input lead and the test data output lead of the linking module;

iii. a decoder connected to the shift register; and

iv. a link update register connected to the decoder and producing enable signals for each core test-access port.

7. The integrated circuit of claim 5 in which the linking module includes:

i. a control module connected to the clock and mode select leads of the IC test access port, and having plural outputs, one output being connected to a select input of the first multiplexer and another output being connected to a select input of the second multiplexer.

ii. a shift register connected to at least two of the control module outputs and serially connected to the test data input lead and the test data output lead of the linking module;

iii. a decorder connected to the shift register; and

iv. a link update register connected to the decoder and producing enable signals for each core test access port.

8. The integrated circuit of claim 7 in which the controller includes an 1149.1 tap controller and additional gates connected to a select lead.

9. The integrated circuit of claim 1 including the test data output lead of at least one core test access port being connected to the test data input lead of the other core test access ports.

10. An integrated circuit comprising:

A. plural core circuits formed in the integrated circuit, each core circuit including a test access port;

B. a test access port for the integrated circuit;

C. a first test linking module coupled between the test access port for the integrated circuit and a first group of the test access ports for the core circuits, the first group of test access ports being less than all of the test access ports for the core circuits; and

D. a second test linking module coupled between the test access port of one core circuit in the first group of test access ports and a second group of test access ports for the core circuits.

11. The integrated circuit of claim 10 including a third test linking module coupled between the test access port of one core circuit in the second group and a third group of test access ports for the core circuits.

12. An integrated circuit comprising;

test interface pads;

a first core circuit including functional circuitry and a test interface circuit, said test interface circuit having a first port and a second port;

a second core circuit contained within the first core circuit, said second core circuit including functional circuitry and a test interface circuit, said test interface circuit having a third port and a fourth port;

a first connection formed between the test interface pads and the first port;

a second connection formed between the second port and the functional circuitry of the first core circuit;

a third connection formed between the second port and the third port; and

a fourth connection formed between the fourth port and functional circuitry of the second core circuit.

13. A process of providing test access to core circuits within an integrated circuit comprising;

performing a first communication to a test interface of a first core circuit, said test interface responsive to said first communication to enable access to a test interface of a second core circuit contained within the first core circuit; and

performing subsequent communications to the test interface of the second core circuit, said subsequent communications enabling the testing of the second core circuit.

14. A process of providing test access to core circuits within an integrated circuit comprising;

performing a first communication to a test interface of a first core circuit, said test interface responsive to said first communication to enable access to a test interface of a second core circuit contained within the first core circuit;

performing a second communication to the test interface of the second core circuit, said test interface of the second core responsive to said second communication to enable access to a test interface of a third core circuit contained within the second core circuit; and

performing subsequent communications to the test interface of the third core circuit, said subsequent communications enabling the testing of the third core circuit.

15. An integrated circuit comprising;

emulation interface pads;

a first core circuit including functional circuitry and an emulation interface circuit, said emulation interface circuit having a first port and a second port;

a second core circuit contained within the first core circuit, said second core circuit including functional circuitry and an emulation interface circuit, said emulation interface circuit having a third port and a fourth port;

a first connection formed between the emulation interface pads and the first port;

a second connection formed between the second port and the functional circuitry of the first core circuit;

a third connection formed between the second port and the third port; and

a fourth connection formed between the fourth port and functional circuitry of the second core circuit.

16. A process of providing emulation access to core circuits within an integrated circuit comprising;

performing a first communication to an emulation interface of a first core circuit, said emulation interface responsive to said first communication to enable access to an emulation interface of a second core circuit contained within the first core circuit; and

performing subsequent communications to the emulation interface of the second core circuit, said subsequent communications enabling the emulation of the second core circuit.

17. A process of providing emulation access to core circuits within an integrated circuit comprising;

performing a first communication to an emulation interface of a first core circuit, said emulation interface responsive to said first communication to enable access to an emulation interface of a second core circuit contained within the first core circuit;

performing a second communication to the emulation interface of the second core circuit, said emulation interface of the second core responsive to said second communication to enable access to an emulation interface of a third core circuit contained within the second core circuit; and

performing subsequent communications to the emulation interface of the third core circuit, said subsequent communications enabling the emulation of the third core circuit.