RAM functional test facilitation circuit with reduced scale
First Claim
1. A circuit for facilitating a functional test on a RAM, said RAM having a plurality of data inputs, address inputs and data outputs, comprising:
- a plurality of first selectors each having first and second inputs and an output for selectively outputting a signal on said first or second input according to a mode signal, said first input thereof receiving a data signal in a normal mode, said outputs of said plurality of first selectors being connected to respective said data inputs of said RAM;
a first scan flip-flop having a data input, a scan in, a scan enable input, a data output and a scan out, said data output thereof being commonly connected to ones of said second inputs of said plurality of first selectors;
a plurality of second selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said mode signal, said first inputs of said plurality of second selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of second selectors being connected to respective said outputs of said plurality of first selectors; and
a plurality of second scan flip-flops each having a data input, a scan in, a scan enable input, a data output and a scan out, said data input thereof being connected to said respective outputs of said second selectors;
wherein said first scan flip-flop and said plurality of second scan flip-flops are cascaded with respect to said scan ins and scan outs thereof to constitute a scan register driven by a clock when a scan enable signal is active, said scan enable signal being provided to said scan enable inputs of said first scan flip-flop and said plurality of second scan flip-flops.
2 Assignments
0 Petitions
Accused Products
Abstract
The outputs of selectors 230 to 23N are respectively connected to the data inputs DI0 to DIN of a RAM 10A. One inputs of selectors 540 to 54N are respectively connected to the data outputs DO0 to DON of the RAM 10A, the other inputs are connected to corresponding outputs of the selectors 230 to 23N. The outputs of the selectors 540 to 54N are connected to data inputs D of respective scan flip-flops 520 to 52N. Not in a RAM test mode, data input lines 210 to 21N are selected by the selectors 230 to 23N to provide to the data inputs DI0 to DIN of the RAM 10A and to the scan flip-flops 520 to 52N through the selectors 540 to 54N, respectively.
11 Citations
18 Claims
-
1. A circuit for facilitating a functional test on a RAM, said RAM having a plurality of data inputs, address inputs and data outputs, comprising:
-
a plurality of first selectors each having first and second inputs and an output for selectively outputting a signal on said first or second input according to a mode signal, said first input thereof receiving a data signal in a normal mode, said outputs of said plurality of first selectors being connected to respective said data inputs of said RAM;
a first scan flip-flop having a data input, a scan in, a scan enable input, a data output and a scan out, said data output thereof being commonly connected to ones of said second inputs of said plurality of first selectors;
a plurality of second selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said mode signal, said first inputs of said plurality of second selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of second selectors being connected to respective said outputs of said plurality of first selectors; and
a plurality of second scan flip-flops each having a data input, a scan in, a scan enable input, a data output and a scan out, said data input thereof being connected to said respective outputs of said second selectors;
wherein said first scan flip-flop and said plurality of second scan flip-flops are cascaded with respect to said scan ins and scan outs thereof to constitute a scan register driven by a clock when a scan enable signal is active, said scan enable signal being provided to said scan enable inputs of said first scan flip-flop and said plurality of second scan flip-flops. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. An integrated circuit devise comprising:
-
a circuit for facilitating a functional test on a RAM, said RAM having a plurality of data inputs, address inputs and data outputs, said circuit for facilitating comprising;
a plurality of first selectors each having first and second inputs and an output for selectively outputting a signal on said first or second input according to a mode signal, said first input thereof receiving a data signal in a normal mode, said outputs of said plurality of first selectors being connected to respective said data inputs of said RAM;
a first scan flip-flop having a data input, a scan in, a scan enable input, a data output and a scan out, said data output thereof being commonly connected to ones of said second inputs of said plurality of first selectors;
a plurality of second selectors each having first and second inputs and an output for selectively outputting a signal on this first or second input according to said mode signal, said first inputs of said plurality of second selectors being connected to respective said data outputs of said RAM, said second inputs of said plurality of second selectors being connected to respective said outputs of said plurality of first selectors; and
a plurality of second scan flip-flops each having a data input, a scan in, a scan enable input, a data output and a scan out, said data input thereof being connected to said respective outputs of said second selectors;
wherein said first scan flip-flop and said plurality of second scan flip-flops are cascaded with respect to said scan ins and scan outs thereof to constitute a scan register driven by a clock when a scan enable signal is active, said scan enable signal being provided to said scan enable inputs of said first scan flip-flop and said plurality of second scan flip-flops;
said integrated circuit devise further comprising;
another selector having first and second inputs and an output for selectively outputting a signal on said first or second input according to said test mode signal, said output thereof being connected to a scan in of said scan register; and
a logic circuit including a combinational circuit and another scan register having a scan out connected to said first input of said another selector;
wherein RAM test serial data is provided to said second input of said another selector without passing through said another scan register. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
Specification