Semiconductor Device

• US 20020163036A1
• Filed: 09/18/2001
• Published: 11/07/2002
• Est. Priority Date: 05/01/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Abe, Yuji, Miura, Naruhisa, Oishi, Toshiyuki, Sugihara, Kohei
• Granted Patent: US 6,633,070 B2
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A field-effect transistor including a gate electrode, silicon layers and source/drain regions is formed at a surface of a silicon substrate. Sidewall insulating films formed on the opposite side surfaces of the gate electrode are provided at portions located between the gate electrode and the silicon layers with voids, respectively. A semiconductor device having a field-effect transistor capable of fast operation is formed.

Claims

1. A semiconductor device comprising:

a gate electrode formed on a surface of a semiconductor substrate with a gate insulating film therebetween;

sidewall insulating films formed on opposite side surfaces of said gate electrode, respectively; and

source/drain regions formed on one and the other of regions of said semiconductor substrate spaced from each other with said gate electrode and said sidewall insulating films therebetween, and each including a portion formed at the surface of said semiconductor substrate and a raised portion formed on the surface of said portion formed at the semiconductor substrate surface, wherein

said sidewall insulating film is provided at its portion located between said raised portion and said gate electrode with a void.

2. The semiconductor device according to claim 1, wherein

said raised portion has a height substantially two or more times larger than a thickness of said sidewall insulating film on the surface of said semiconductor substrate.

3. The semiconductor device according to claim 1, wherein

said gate electrode has a wide portion located closer to said raised portion.

4. The semiconductor device according to claim 3, wherein

said wide portion has a lower end located substantially at a level equal to or lower than the top surface of said raised portion.

5. The semiconductor device according to claim 1, wherein

said gate electrode is formed of at least two layers, and

the upper layer of said two layers includes said wide portion.

6. The semiconductor device according to claim 5, wherein

said upper layer of said gate electrode is made of silicon, and said lower layer is made of silicon germanium.

7. The semiconductor device according to claim 5, wherein

said upper layer of said gate electrode contains metal, and said lower layer contains a semiconductor layer.

8. The semiconductor device according to claim 5, wherein

said wide portion has the lower end located at the level equal to or lower than the top surface of said raised portion.

9. The semiconductor device according to claim 1, further comprising:

an interlayer insulating film formed on said semiconductor substrate and covering said sidewall insulating films and said source/drain regions, wherein

said interlayer insulating film has the top surface portion located closer to the gate electrode.

10. The semiconductor device according to claim 9, wherein

said gate electrode is made of metal.

11. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate electrode on a surface of a semiconductor substrate;

forming a dummy sidewall insulating film on each of the opposite side surfaces of said gate electrode;

forming impurity regions partially forming source/drain regions on one and the other of regions of said semiconductor substrate spaced from each other with said gate electrode and said dummy sidewall insulating films therebetween;

forming raised portions partially forming said source/drain regions on the surfaces of the impurity regions, respectively;

removing said dummy sidewall insulating films after forming said raised portions; and

forming sidewall insulating films on the side surfaces of said gate electrode, respectively, after removing said dummy sidewall insulating films, wherein

said step of forming said sidewall insulating film is performed to form a void in a region between said raised portion and said gate electrode by suppressing supply of a material of said sidewall insulating film to said region between said raised portion and said gate electrode.

12. The method of manufacturing the semiconductor device according to claim 11, wherein

said step of forming said dummy sidewall insulating film is performed to form said dummy sidewall insulating film provided with a wide portion extending from a surface of said semiconductor substrate to a predetermined height and having a larger film thickness than the other portion, and

said step of forming said raised portion is performed to provide said raised portion extending beyond said wide portion.

13. The method of manufacturing the semiconductor device according to claim 12, further comprising the step of:

removing a portion of said raised portion extending beyond said wide portion after forming said sidewall insulating film.

14. The method of manufacturing the semiconductor device according to claim 11, further comprising, after said step of forming said raised portion and before said step of removing said dummy sidewall insulating film, the steps of:

forming an interlayer insulating film covering said gate electrode, said dummy sidewall insulating film and said raised portion; and

processing said interlayer insulating film to expose said gate electrode and said dummy sidewall insulating film, wherein

said step of removing said dummy sidewall insulating film is performed to remove said dummy sidewall insulating film by effecting etching on the exposed portion of said dummy sidewall insulating film.

15. The method of manufacturing the semiconductor device according to claim 14, further comprising, after said step of exposing said gate electrode and said dummy sidewall insulating film and before said step of removing said dummy sidewall insulating film, the steps of:

removing said gate electrode to expose the surface of said semiconductor substrate; and

forming a new gate electrode including a metal film on the exposed surface of said semiconductor substrate, wherein

said step of removing said dummy sidewall insulating film is performed to remove said dummy sidewall insulating film by effecting etching on a portion of said dummy sidewall insulating film exposed and located between said new gate electrode and said interlayer insulating film.