Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed

• US 20020164840A1
• Filed: 05/01/2001
• Published: 11/07/2002
• Est. Priority Date: 05/01/2001
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lin, Jyh-Rong, Lu, Ming, Lu, Szu-Wei
• Granted Patent: US 6,605,525 B2
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafer during the same process used for forming the metal vias. The metal lines are subsequently removed by either a mechanical method such as dicing with a diamond saw or by a chemical method such as wet etching. The method allows the fabrications of a wafer level package that has a multiplicity of elastomeric blocks formed on top as stress buffering layer without the CTE mismatch problem with other layers on the wafer.

Claims

1. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks comprising the steps of:

providing a wafer that is pre-processed with a plurality of IC dies formed on a top surface, each of said plurality of IC dies being spaced-apart from its immediately adjacent IC dies by a distance that is at least a width of a scribe line, each of said plurality of IC dies further having a multiplicity of input/output pads formed on top;

depositing a first metal layer on said top surface of the wafer;

depositing a photoresist later of at least 20 μ

m thickness on said first metal layer;

forming a plurality of trench openings separating said plurality if IC dies and a plurality of via openings with each on one of said multiplicity of input/output pads exposing said first metal layer;

depositing a second metal into and filling said plurality of trench openings forming a plurality of metal lines and said plurality of via openings forming a plurality of metal vias;

removing said photoresist layer and said first metal layer not covered by said plurality of metal vias; and

depositing an elastomeric material on top of said wafer filling cavities formed between said plurality of metal lines forming said multiplicity of elastomeric blocks.

2. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1 further comprising the steps after the deposition of said elastomeric material:

depositing a first insulating material layer on top of said multiplicity of elastomeric blocks;

depositing a third metal on top of said first insulating material layer and forming into conductive leads for input/output redistribution; and

depositing a second insulating material layer on top of said conductive leads and said first insulating material layer.

3. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1 further comprising the steps of after the deposition of said second insulating material layer:

forming a plurality of openings in said second insulating material layer exposing said third metal layer forming a plurality of input/output redistribution pads; and

forming a plurality of solder bumps on said plurality of input/output redistribution pads.

4. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 3 further comprising the step of forming under-bump-metallurgy (UBM) layers on said plurality of input/output redistribution pads before the formation of said plurality of solder bumps.

5. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1 further comprising the step of depositing said first metal layer with a metal of Cu, Al or alloys thereof.

6. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1 further comprising the step of depositing said photoresist layer to a thickness between about 20 μ

m and about 200 μ

m.

7. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1 further comprising the step of depositing said second metal with a metal of Cu, Al or alloys thereof.

8. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1, wherein said formation step for said plurality of trench openings and said plurality of via openings further comprising the steps of photolithography and dry etching.

9. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 1 further comprising the step of depositing said elastomeric material by a printing technique or by a spin-coating technique.

10. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 3 further comprising the step of forming said plurality of solder bumps by a technique selected from the group consisting of printing, electroplating and electroless plating.

11. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 3 further comprising the step of forming said plurality of solder bumps with a solder material containing Pb and Sn.

12. A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks according to claim 3 further comprising the step of severing said plurality of IC dies by a mechanical means or by wet etching.

14. A wafer level package having a multiplicity of elastomeric blocks on top according to claim 13 further comprising:

a first insulating material layer on top of said multiplicity of elastomeric blocks;

a plurality of conductive leads for input/output redistribution wherein one end of each of the plurality of conductive leads being in electrical communication with one of said plurality of metal vias; and

a second insulating material layer on top of said plurality of conductive leads and said first insulating material layer.

15. A wafer level package having a multiplicity of elastomeric blocks on top according to claim 14 further comprising:

a plurality of openings in said second insulating material layer exposing said third metal layer forming a plurality of input/output redistributing pads; and

a plurality of solder bumps with each formed on one of said plurality of input/output redistribution pads.

16. A wafer level package having a multiplicity of elastomeric blocks on top according to claim 15 further comprising UBM layers in-between said plurality of input/output redistribution pads and said plurality of solder bumps.

17. A wafer level package having a multiplicity of elastomeric block on top according to claim 15, wherein said plurality of solder bumps being reflown into plurality of solder balls.

18. A wafer level package having a multiplicity of elastomeric blocks on top according to claim 13, wherein said plurality of metal lines being formed of Cu, Al or alloys thereof.

19. A wafer level package having a multiplicity of elastomeric blocks on top according to claim 13, wherein said plurality of metal vias being formed of Cu, Al or alloys thereof.

20. A wafer level package having a multiplicity of elastomeric blocks on top according to claim 13, wherein said elastomeric material has a Young'"'"'s modulus of not higher than 10 MPa.

13. A wafer level package having a multiplicity of elastomeric blocks on top comprising:

a wafer that is pre-processed with a plurality of IC dies formed on a top surface, each of said plurality of IC dies having a multiplicity of input/output pads formed on top;

a plurality of metal lines separating said plurality of IC dies formed on a plurality of scribe lines on said top surface of the wafer;

a plurality of metal vias each in electrical communication with one of said plurality of input/output pads; and

an elastomeric material filling cavities formed in-between said plurality of metal lines forming said multiplicity of elastomeric blocks.