Semiconductor device and manufacturing method thereof
First Claim
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1. A semiconductor device, comprising:
- a first NMOS transistor and a first PMOS transistor provided respectively in a first NMOS region and a first PMOS region defined in a surface of a semiconductor substrate; and
a second NMOS transistor and a second PMOS transistor provided respectively in a second NMOS region and a second PMOS region defined in the surface of said semiconductor substrate;
said second NMOS transistor and said second PMOS transistor having higher operating voltages respectively than said first NMOS transistor and said first PMOS transistor, said second PMOS transistor being a buried-channel type MOS transistor in which a channel is formed in the inside of said semiconductor substrate, and said first NMOS transistor, said first PMOS transistor, and said second NMOS transistor being surface-channel type MOS transistors in which a channel is formed in the surface of said semiconductor substrate.
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Abstract
CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor (100B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).
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Citations
14 Claims
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1. A semiconductor device, comprising:
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a first NMOS transistor and a first PMOS transistor provided respectively in a first NMOS region and a first PMOS region defined in a surface of a semiconductor substrate; and
a second NMOS transistor and a second PMOS transistor provided respectively in a second NMOS region and a second PMOS region defined in the surface of said semiconductor substrate;
said second NMOS transistor and said second PMOS transistor having higher operating voltages respectively than said first NMOS transistor and said first PMOS transistor, said second PMOS transistor being a buried-channel type MOS transistor in which a channel is formed in the inside of said semiconductor substrate, and said first NMOS transistor, said first PMOS transistor, and said second NMOS transistor being surface-channel type MOS transistors in which a channel is formed in the surface of said semiconductor substrate. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device manufacturing method, comprising the steps of:
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(a) defining a first NMOS region and a first PMOS region in a surface of a semiconductor substrate respectively for formation of a first NMOS transistor and a first PMOS transistor, and defining a second NMOS region for formation of a second NMOS transistor having a higher operating voltage than said first NMOS transistor and a second PMOS region for formation of a second PMOS transistor having a higher operating voltage than said first PMOS transistor;
(b) forming a first gate insulating film in said first NMOS region and said first PMOS region, and forming a second gate insulating film thicker than said first gate insulating film in said second NMOS region and said second PMOS region;
(c) forming a P-type impurity layer of a relatively low concentration in the surface of said semiconductor substrate in said second PMOS region;
(d) forming a non-single-crystal silicon film containing an N-type impurity at a relatively high concentration on said first and second gate insulating films;
(e) introducing a P-type impurity at a relatively high concentration only into said non-single-crystal silicon film in said first PMOS region; and
(d) patterning said non-single-crystal silicon film to form gate electrodes respectively in said first NMOS region, said first PMOS region, said second NMOS region, and said second PMOS region. - View Dependent Claims (6, 7)
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8. A semiconductor device manufacturing method, comprising the steps of:
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(a) defining a first NMOS region and a first PMOS region in a surface of a semiconductor substrate respectively for formation of a first NMOS transistor and a first PMOS transistor, and defining a second NMOS region for formation of a second NMOS transistor having a higher operating voltage than said first NMOS transistor and a second PMOS region for formation of a second PMOS transistor having a higher operating voltage than said first PMOS transistor;
(b) forming a first gate insulating film in said first NMOS region and said first PMOS region, and forming a second gate insulating film thicker than said first gate insulating film in said second NMOS region and said second PMOS region;
(c) forming a P-type impurity layer of a relatively low concentration in the surface of said semiconductor substrate in said second PMOS region;
(d) forming a non-single-crystal silicon film containing no impurity on said first and second gate insulating films;
(e) introducing an N-type impurity at a relatively high first concentration only into said non-single-crystal silicon film in said first NMOS region, said second NMOS region, and said second PMOS region; and
(f) forming gate electrodes by using said non-single-crystal silicon film respectively in said first NMOS region, said first PMOS region, said second NMOS region, and said second PMOS region, and introducing a P-type impurity at a relatively high second concentration into the gate electrode formed in said first PMOS region. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification