Circuit board construction

• US 20020166697A1
• Filed: 05/11/2001
• Published: 11/14/2002
• Est. Priority Date: 05/11/2001
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Youngs, Thurston B. Jr., Kresge, John S., Pierson, Mark V., Janecek, Mark L.
• Application Number:
  US09/853,506
• Publication Number:
  US 20020166697A1
• Time in Patent Office: Days
• US Class Current: 174/262
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 3/321 by conductive adhesives
• CPC Class Codes: H05K 3/4069 for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores
• CPC Class Codes: Y10T 29/49126 Assembling bases

Abstract

An improved circuit board construction featuring a multilayered, laminated structure having an intermediate power core layer having conductive adhesive-filled via through holes. The via through holes of the intermediate power core layer make electrical connection with metallic pads of conductive vias of adjacent outer signal core layers when the layers are laminated.

Claims

1. A multi-layered circuit structure, comprising:

a first substrate having conductive via through holes disposed therein; and

a second substrate laminated to said first substrate and having conductive, adhesive-filled via through holes that align with, and make electrical contact with, the conductive via through holes of said first substrate upon lamination of said first and second substrates.

2. The multi-layered circuit structure in accordance with claim 1, wherein said first substrate comprises a signal core layer, and said second substrate comprises a power core layer.

3. The multi-layered circuit structure in accordance with claim 1, wherein said first substrate comprises a pair of outer signal core layers, and said second substrate comprises an inner power core layer sandwiched between said pair of outer signal core layers.

4. The multi-layered circuit structure in accordance with claim 3, wherein said via through holes of said inner power core layer comprise undercut contact surfaces, and said via through holes of said signal layer have metallic pads that make electrical contact with said undercut contact surfaces of said via through holes of said inner power core layer.

5. A multi-layered circuit structure, comprising:

a first substrate having conductive via through holes disposed therein; and

a second substrate laminated to said first substrate, and having via through holes comprising conductive adhesive coated pads that align with, and make electrical contact with, the conductive via through holes of said first substrate upon lamination of said first and second substrates.

6. The multi-layered circuit structure in accordance with claim 5, wherein said first substrate comprises a signal core layer, and said second substrate comprises a power core layer.

7. The multi-layered circuit structure in accordance with claim 5, wherein said first substrate comprises a pair of outer signal core layers, and said second substrate comprises an inner power core layer sandwiched between said pair of outer signal core layers.

8. A method of fabricating a multi-layered circuit, comprising the steps of:

filling via through holes of a first substrate with conductive adhesive;

aligning said via through holes of said first substrate with conductive via through holes of a second substrate; and

laminating together said first and second substrates.

9. The method in accordance with claim 8, wherein said first substrate comprises a signal core layer, and said second substrate comprises a power core layer.

10. The method in accordance with claim 8, wherein said first substrate comprises a pair of outer signal core layers, and said second substrate comprises an inner power core layer sandwiched between said pair of outer signal core layers.