Solid state imaging device, method of manufacturing the same, and solid state imaging system

• US 20020167030A1
• Filed: 06/21/2002
• Published: 11/14/2002
• Est. Priority Date: 12/01/1999
• Status: Active Grant

• Current Assignee: Innotech Corp.
• Original Assignee: Takashi Miida
• Inventors: Miida, Takashi
• Granted Patent: US 6,656,777 B2
• Time in Patent Office: Days
• US Class Current: 257/215
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type

Abstract

There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.

Claims

1. A solid state imaging device comprising:

a photo diode formed in a second semiconductor layer of opposite conductivity type in a first semiconductor layer of one conductivity type; and

a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer of opposite conductivity type in a third semiconductor layer of one conductivity type adjacently to the photo diode;

wherein a portion of the photo diode comprises an impurity region of one conductivity type on a surface layer of the second semiconductor layer, and a portion of the insulated gate field effect transistor comprises a source region and a drain region of one conductivity type on a surface layer of the fourth semiconductor layer, a channel region between the source region and the drain region, a high concentration buried layer of opposite conductivity type in a neighborhood of the source region in the fourth semiconductor layer under the channel region, and a gate electrode formed over the channel region via a gate insulating film,

the impurity region is connected to the drain region, the first semiconductor layer is connected to the third semiconductor layer, and the second semiconductor layer is connected to the fourth semiconductor layer, and

a portion of the first semiconductor layer under the second semiconductor layer is thicker than a portion of the third semiconductor layer under the fourth semiconductor layer in a depth direction.

2. A solid state imaging device according to claim 1, wherein the first semiconductor layer is formed on a first base layer of opposite conductivity type, and the third semiconductor layer is formed on a second base layer of opposite conductivity type connected to the first base layer.

3. A solid state imaging device according to claim 2, wherein the first base layer is formed of a substrate made of a semiconductor of opposite conductivity type, and the first semiconductor layer consists of a fifth semiconductor layer containing a one conductivity type buried layer and a one conductivity type well region on the fifth semiconductor layer, and

the second base layer consists of a substrate made of a semiconductor of opposite conductivity type and a sixth semiconductor layer containing a one conductivity type buried layer on the substrate, and the third semiconductor layer is formed of the one conductivity type well region.

4. A solid state imaging device according to claim 1, wherein the high concentration buried layer is formed in a partial region on a source region side in a channel length direction extended from the drain region to the source region.

5. A solid state imaging device according to claim 1, wherein the high concentration buried layer is formed to extend over a channel width direction.

6. A solid state imaging device according to claim 1, wherein the gate electrode of the insulated gate field effect transistor has a ring-like shape, the source region is formed on a surface layer of the fourth semiconductor layer to be surrounded by the gate electrode, the drain region is formed on a surface layer of the fourth semiconductor layer to surround the gate electrode.

7. A solid state imaging device according to claim 1, wherein the gate electrode and its peripheral region of the insulated gate field effect transistor is light-shielded.

8. A solid state imaging device according to claim 1, wherein a load circuit is connected to the source region of the insulated gate field effect transistor to form a source follower circuit.

9. A solid state imaging device according to claim 8, wherein a source output of the source follower circuit is connected to a video signal output terminal.

11. A method of manufacturing a solid state imaging device, according to claim 1, wherein the gate electrode has a ring-like shape, the source region is formed on a surface layer of the second well region surrounded by the gate electrode, the drain region is formed on a surface layer of the second well region to surround the gate electrode.

13. A solid state imaging device according to claim 12, wherein the first semiconductor layer is formed on a first base layer of opposite conductivity type, and the third semiconductor layer is formed on a second base layer of opposite conductivity type that is connected to the first base layer.

14. A solid state imaging device according to claim 13, wherein the first base layer is formed of a substrate made of a semiconductor of opposite conductivity type, and the first semiconductor layer consists of a fifth semiconductor layer containing a one conductivity type buried layer and a one conductivity type well region on the fifth semiconductor layer, and

the second base layer consists of a substrate made of a semiconductor of opposite conductivity type and a sixth semiconductor layer containing an opposite conductivity type buried layer on the substrate, and the third semiconductor layer is formed of the one conductivity type well region.

15. A solid state imaging device according to claim 12, wherein the high concentration buried layer is formed a partial region on a source region side in a channel length direction extended from the drain region to the source region.

16. A solid state imaging device according to claim 12, wherein the high concentration buried layer is formed to extend over a channel width direction.

17. A solid state imaging device according to claim 12, wherein the gate electrode of the insulated gate field effect transistor has a ring-like shape, the source region is formed on a surface layer of the fourth semiconductor layer to be surrounded by the gate electrode, the drain region is formed on a surface layer of the fourth semiconductor layer to surround the gate electrode.

18. A solid state imaging device according to claim 12, wherein the gate electrode and its peripheral region of the insulated gate field effect transistor is light-shielded.

19. A solid state imaging device according to claim 12, wherein a load circuit is connected to the source region of the insulated gate field effect transistor to form a source follower circuit.

20. A solid state imaging device according to claim 19, wherein a source output of the source follower circuit is connected to a video signal output terminal.

10. A method of manufacturing a solid state imaging device, comprising the steps of:

forming a first buried layer of one conductivity type in an interior of a seventh semiconductor layer of opposite conductivity type by introducing one conductivity type impurity into the seventh semiconductor layer by using a first mask;

forming a first well region of opposite conductivity type on a surface layer of the seventh semiconductor layer and over the first buried layer by introducing opposite conductivity type impurity into the seventh semiconductor layer by using the first mask;

forming a one conductivity type region to be connected to the first buried layer and to contain the first well region by introducing one conductivity type impurity into the surface layer of the seventh semiconductor layer;

forming a second buried layer of opposite conductivity type, that has higher impurity concentration than the seventh semiconductor layer, under the one conductivity type region by introducing opposite conductivity type impurity in an interior of the seventh semiconductor layer by using a second mask;

forming a second well region of opposite conductivity type, that is connected to the first well region, by introducing opposite conductivity type impurity on a surface layer of the one conductivity type region and over the second buried layer by using the second mask;

forming a channel doped layer of one conductivity type by introducing one conductivity type impurity on a surface layer of the second well region by using the second mask;

forming a high concentration buried layer of opposite conductivity type, that has higher impurity concentration than the second well region, in an interior of the second well region under the channel doped layer by introducing opposite conductivity type impurity in an interior of the second well region by using a third mask;

forming a gate insulating film on the seventh semiconductor layer by a thermal oxidation;

forming a gate electrode on the gate insulating film to cover the high concentration buried layer and to bring the high concentration buried layer close to a source region side; and

forming a source region and a drain region of one conductivity type on a surface layer of the second well region on both sides of the gate electrode and forming an impurity region on a surface layer of the first well region.

12. A solid state imaging device comprising:

a photo diode formed in a second semiconductor layer of opposite conductivity type in a first semiconductor layer of one conductivity type; and

a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer of opposite conductivity type in a third semiconductor layer of one conductivity type adjacently to the photo diode;

wherein a portion of the photo diode comprises an impurity region of one conductivity type on a surface layer of the second semiconductor layer, and a portion of the insulated gate field effect transistor comprises a source region and a drain region of one conductivity type on a surface layer of the fourth semiconductor layer, a channel region between the source region and the drain region, a gate electrode over the channel region via a gate insulating film, and a high concentration buried layer of opposite conductivity type in the fourth semiconductor layer in a neighborhood of the source region under the channel region,

the first semiconductor layer is connected to the third semiconductor layer, and the second semiconductor layer is connected to the fourth semiconductor layer, a portion of the insulated gate field effect transistor has a low concentration drain (LDD) structure, and the low concentration drain region is extended to form the impurity region that has impurity concentration substantially identical to the low concentration drain region.

29. A solid state imaging system having a solid state imaging device set forth in any one of claims 12 to 20.

21. A method of manufacturing a solid state imaging device, comprising the steps of:

forming a first buried layer of one conductivity type in an interior of a seventh semiconductor layer of opposite conductivity type by introducing one conductivity type impurity into the seventh semiconductor layer by using a first mask;

forming a first well region of opposite conductivity type on a surface layer of the seventh semiconductor layer and over the first buried layer by introducing opposite conductivity type impurity into the seventh semiconductor layer by using the first mask;

forming a one conductivity type region to be connected to the first buried layer and to contain the first well region by introducing one conductivity type impurity into the surface layer of the seventh semiconductor layer;

forming a second buried layer of opposite conductivity type, that has higher impurity concentration than the seventh semiconductor layer, under the one conductivity type region by introducing opposite conductivity type impurity in an interior of the seventh semiconductor layer by using a second mask;

forming a second well region of opposite conductivity type, that is connected to the first well region, by introducing opposite conductivity type impurity on a surface layer of the one conductivity type region and over the second buried layer by using the second mask;

forming a channel doped layer of one conductivity type by introducing one conductivity type impurity on a surface layer of the second well region by using the second mask;

forming a high concentration buried layer of opposite conductivity type, that has higher impurity concentration than the second well region, in an interior of the second well region under the channel doped layer by introducing opposite conductivity type impurity in an interior of the second well region by using a third mask;

forming a gate insulating film on the seventh semiconductor layer by a thermal oxidation;

forming a gate electrode on the gate insulating film to cover the high concentration buried layer and to bring the high concentration buried layer close to a source region side;

forming an impurity region of one conductivity type on a surface layer of the first well region at a same time of forming a source region and a drain region of one conductivity type on a surface layer of the second well region on both sides of the gate electrode by introducing one conductivity type impurity on a surface layer of the seventh semiconductor layer;

forming sidewalls on side surfaces of the gate electrode; and

forming a resist film to cover a part of the impurity region acting as a light receiving portion, and then forming a contact layer that comes into contact with the drain region and has higher concentration than the drain region by introducing one conductivity impurity by using the gate electrode, the sidewalls, and the resist film as a mask.

22. A solid state imaging device manufacturing method according to claim 21, wherein the first buried layer and the first well region are formed by using a first mask in a same planar position and a different depth respectively, and the second buried layer, the second well region, and the channel doped layer are formed by using a second mask in a same planar position and a different depth respectively.

23. A solid state imaging device manufacturing method according to claim 21, wherein a MOS transistor that constitutes a CMOS circuit for driving the solid state imaging device and has a low concentration drain (LDD) structure is formed on a same substrate as the solid state imaging device, and the drain region is formed at a same time when a low concentration drain region of the MOS transistor in the CMOS circuit is formed.

24. A solid state imaging device manufacturing method according to claim 21, wherein a MOS transistor that constitutes a CMOS circuit for driving the solid state imaging device and has a low concentration drain (LDD) structure is formed on a same substrate as the solid state imaging device, and the contact layer is formed at a same time when a high concentration drain region of the MOS transistor in the CMOS circuit is formed.

25. A solid state imaging device manufacturing method according to claim 21, wherein the gate electrode has a ring-like shape, the source region is formed on a surface layer of the second well region surrounded by the gate electrode, and the drain region is formed on a surface layer of the second well region to surround the gate electrode.

27. A solid state imaging device manufacturing method according to claim 26, wherein the second well layer and the channel doped layer are formed by using a same mask in a same planar position and a different depth respectively.

28. A solid state imaging device manufacturing method according to claim 26, wherein the gate electrode has a ring-like shape, the source region is formed on a surface layer of the second well region surrounded by the gate electrode, and the drain region is formed on a surface layer of the second well region to surround the gate electrode.

26. A solid state imaging device manufacturing method comprising the steps of:

forming a first well region of opposite conductivity type on a surface layer of one conductivity type region by introducing an opposite conductivity type impurity into the one conductivity type region of a surface layer of a semiconductor substrate;

forming a second well region of opposite conductivity type connected to the first well region by introducing the opposite conductivity type impurity into a surface layer of the one conductivity type region;

forming a channel doped layer of one conductivity type by introducing a one conductivity type impurity into a surface layer of the second well region;

forming a high concentration buried layer of opposite conductivity type, that has an impurity concentration higher than the second well region, in an inside of the second well region under the channel doped layer by introducing the opposite conductivity type impurity into an inside of the second well region;

forming a gate insulating film by thermally oxidizing a surface of the semiconductor substrate;

forming a gate electrode on the gate insulating film to cover the high concentration buried layer and to bring the high concentration buried layer close to a source region side;

forming one conductivity type source/drain regions on a surface layer of the second well region on both sides of the gate electrode and simultaneously forming a one conductivity type impurity region on a surface layer of the first well region, by introducing the one conductivity type impurity into a surface of the semiconductor substrate; and

forming a resist film to cover a part of the impurity region acting as a light receiving portion, and then forming a high concentration contact layer, that comes in contact with the drain region and has a concentration higher than the drain region, by introducing the one conductivity type impurity while using the gate electrode and the resist film as a mask.