Hybrid semiconductor structure and device

• US 20020167070A1
• Filed: 07/01/2002
• Published: 11/14/2002
• Est. Priority Date: 06/30/2000
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Prendergast, E. James
• Application Number:
  US10/184,803
• Publication Number:
  US 20020167070A1
• Time in Patent Office: Days
• US Class Current: 257/613
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/31691 with perovskite structure

Abstract

Islands of compound semiconductor material can be formed in silicon wafers by etching wells into the silicon wafer, growing an accommodating layer on the silicon wafer, and then growing a compound semiconductor layer on the accommodating layer. The accommodating layer may be a layer of monocrystalline oxide and an amorphous interface layer of silicon oxide separating the monocrystalline oxide from the silicon wafer. The layer or layers that make up the accommodating layer can be annealed to form a single amorphous layer. A template layer may be grown between the accommodating layer and the monocrystalline compound semiconductor layer. The various layers follow the contours of the wells in the silicon wafer. A polishing step removes the various layers except in the wells, leaving a flat silicon surface having islands of monocrystalline compound semiconductor material separated from the silicon by the accommodating layer, and by the template layer if present. Electronic components may be formed in the silicon and/or the monocrystalline compound semiconductor material.

Claims

1. A hybrid semiconductor structure comprising:

a monocrystalline semiconductor substrate having a substantially flat surface, said substantially flat surface having at least one well therein;

an accommodating layer overlying said monocrystalline semiconductor substrate in said at least one well; and

a monocrystalline compound semiconductor material overlying said accommodating layer in said at least one well.

2. The hybrid semiconductor structure of claim 1 wherein said accommodating layer insulates said monocrystalline compound semiconductor material from said monocrystalline semiconductor substrate.

3. The hybrid semiconductor structure of claim 1 wherein said monocrystalline compound semiconductor material in said at least one well has a face facing away from said accommodating layer, said face being substantially flush with said substantially flat surface.

4. The hybrid semiconductor structure of claim 1 wherein said monocrystalline semiconductor substrate comprises a monocrystalline Group IV material.

5. The hybrid semiconductor structure of claim 4 wherein said monocrystalline Group IV material is silicon.

6. The hybrid semiconductor structure of claim 1 wherein said monocrystalline compound semiconductor material is selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe and ZnSeS.

7. The hybrid semiconductor structure of claim 1 wherein said accommodating layer comprises a monocrystalline oxide material.

8. The hybrid semiconductor structure of claim 7 wherein said monocrystalline oxide material comprises Sr_zBa_1-zTiO₃, where z ranges from 0 to 1.

9. The hybrid semiconductor structure of claim 7 wherein said accommodating layer further comprises an amorphous layer adjacent said monocrystalline semiconductor substrate.

10. The hybrid semiconductor structure of claim 9 wherein said amorphous layer comprises a silicon oxide.

11. The hybrid semiconductor structure of claim 9 wherein said accommodating layer is annealed.

12. The hybrid semiconductor structure of claim 1 wherein said accommodating layer comprises a monocrystalline nitride material.

13. The hybrid semiconductor structure of claim 12 wherein said accommodating layer further comprises an amorphous layer adjacent said monocrystalline semiconductor substrate.

14. The hybrid semiconductor structure of claim 13 wherein said amorphous layer comprises a silicon oxide.

15. The hybrid semiconductor structure of claim 13 wherein said accommodating layer is annealed.

16. The hybrid semiconductor structure of claim 1 further comprising a template layer between said accommodating layer and said monocrystalline compound semiconductor material.

18. The method of claim 17 wherein said providing comprises providing a monocrystalline semiconductor substrate comprising a monocrystalline Group IV material.

19. The method of claim 18 wherein said providing comprises providing a monocrystalline semiconductor substrate comprising monocrystalline silicon.

20. The method of claim 17 wherein said forming comprises etching.

21. The method of claim 20 wherein said etching comprises wet etching.

22. The method of claim 20 wherein said etching comprises dry etching.

23. The method of claim 18 wherein said overlaying comprises overlaying said accommodating layer with a monocrystalline compound semiconductor material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe and ZnSeS.

24. The method of claim 16 wherein said depositing comprises depositing an accommodating layer comprising a monocrystalline oxide material.

25. The method of claim 24 wherein said depositing comprises depositing an accommodating layer comprising a monocrystalline oxide material comprising Sr_zBa_1-zTiO₃, where z ranges from 0 to 1.

26. The method of claim 24 wherein said depositing further comprises forming an amorphous layer adjacent said monocrystalline semiconductor substrate.

27. The method of claim 26 wherein said forming an amorphous layer comprises forming an amorphous layer comprising a silicon oxide.

28. The method of claim 26 wherein said depositing further comprises annealing said accommodating layer.

29. The method of claim 16 wherein said depositing comprises depositing an accommodating layer comprising a monocrystalline nitride material.

30. The method of claim 29 wherein said depositing further comprises forming an amorphous layer adjacent said monocrystalline semiconductor substrate.

31. The method of claim 30 wherein said forming an amorphous layer comprises forming an amorphous layer comprising a silicon oxide.

32. The method of claim 30 wherein said depositing further comprises annealing said accommodating layer.

33. The method of claim 17 further comprising depositing a template layer between said buffer layer and said monocrystalline compound semiconductor material.

35. The hybrid semiconductor device of claim 34 wherein said accommodating layer insulates said monocrysalline compound semiconductor material from said monocrystalline semiconductor substrate.

36. The hybrid semiconductor device of claim 34 wherein said monocrystalline compound semiconductor material in said at least one well has a face facing away from said accommodating layer, said face being substantially flush with said substantially flat surface.

37. The hybrid semiconductor device of claim 34 wherein said monocrystalline semiconductor substrate comprises a monocrystalline Group IV material.

38. The hybrid semiconductor device of claim 37 wherein said monocrystalline Group IV material is silicon.

39. The hybrid semiconductor device of claim 34 wherein said monocrystalline compound semiconductor material is selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe and ZnSeS.

40. The hybrid semiconductor device of claim 34 wherein said accommodating layer comprises a monocrystalline oxide material.

41. The hybrid semiconductor device of claim 40 wherein said monocrystalline oxide material comprises Sr_zBa_1-zTiO₃, where z ranges from 0 to 1.

42. The hybrid semiconductor device of claim 40 wherein said accommodating layer further comprises an amorphous layer adjacent said monocrystalline semiconductor substrate.

43. The hybrid semiconductor device of claim 42 wherein said amorphous layer comprises a silicon oxide.

44. The hybrid semiconductor device of claim 42 wherein said accommodating layer is annealed.

45. The hybrid semiconductor device of claim 34 wherein said accommodating layer comprises a monocrystalline nitride material.

46. The hybrid semiconductor device of claim 45 wherein said accommodating layer further comprises an amorphous layer adjacent said monocrystalline semiconductor substrate.

47. The hybrid semiconductor device of claim 46 wherein said amorphous layer comprises a silicon oxide.

48. The hybrid semiconductor device of claim 46 wherein said accommodating layer is annealed.

49. The hybrid semiconductor device of claim 34 further comprising a template layer between said accommodating layer and said monocrystalline compound semiconductor material.

17. A method for making a hybrid semiconductor structure, said method comprising:

providing a monocrystalline semiconductor substrate having a substantially flat surface;

forming at least one well in said substantially flat surface;

depositing an accommodating layer on said substantially flat surface of said monocrystalline semiconductor substrate and in said at least one well;

overlaying said accommodating layer with a monocrystalline compound semiconductor material; and

polishing said hybrid semiconductor structure down to said substantially flat surface, thereby removing said monocrystalline compound semiconductor material except from said at least one well.

34. A hybrid semiconductor device comprising:

a monocrystalline semiconductor substrate having a substantially flat surface, said substantially flat surface having at least one well therein;

an accommodating layer overlying said monocrystalline semiconductor substrate in said at least one well;

a monocrystalline compound semiconductor material overlying said accommodating layer in said at least one well; and

a plurality of electronic components;

wherein;

at least one of said electronic components is formed at least partially in or on said monocrystalline semiconductor substrate; and

at least one of said electronic components is formed at least partially in or on said monocrystalline compound semiconductor material.