Signal reception circuit, data transfer control device and electronic equipment

• US 20020167342A1
• Filed: 05/10/2002
• Published: 11/14/2002
• Est. Priority Date: 05/14/2001
• Status: Active Grant

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Nakada, Akira
• Granted Patent: US 6,833,738 B2
• Time in Patent Office: Days
• US Class Current: 327/58
• CPC Class Codes: H03K 5/082 with an adaptive threshold
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02

Abstract

A signal reception circuit capable of detecting and receiving a signal at a high speed having small amplitude, and a data transfer control device and electronic equipment using the same. A differential pair of reception signals DP and DM is detected by an HS_SQ_L circuit for low speed having high receiving sensitivity and an HS_SQ circuit for high speed having high speed response performance. In the case of a high-speed reception signal, a logical product of a signal HS_DataIn fetched by an HS differential data receiver and a signal HS_SQ indicating the result of signal detection by the HS_SQ circuit for high speed is supplied to a DLL circuit. In the case of a low-speed reception signal, an FS differential receiver is activated after the detection of differential pair of reception signals DP and DM by the HS_SQ_L circuit for low speed. A signal FS_DataIn fetched by the FS differential receiver is supplied to an FS circuit.

Claims

1. A signal reception circuit for receiving a differential pair of input signals, comprising:

first and second reception circuits which receive a differential pair of input signals to generate first and second reception signals;

a first signal detection circuit which detects the differential pair of input signals based on a first reference level, in a first mode for high speed; and

a second signal detection circuit which detects the differential pair of input signals based on a second reference level which is higher than the first reference level, in a second mode for low speed,

wherein the first reception signal is enabled when the differential pair of input signals is detected by the first signal detection circuit; and

wherein the second reception signal is enabled when the differential pair of input signals is detected by the second signal detection circuit.

2. The signal reception circuit as defined in claim 1, further comprising:

a mask circuit which masks the first reception signal according to the detection result of the first signal detection circuit,

wherein operation of the second reception circuit is controlled based on the result of detection performed by the second signal detection circuit.

3. The signal reception circuit as defined in claim 1,

wherein the second mode shifts to the first mode, based on the second reception signal which has been enabled in the second mode.

4. The signal reception circuit as defined in claim 1,

wherein the first mode is the High Speed mode of the Universal Serial Bus (USB) 2.0 standard;

wherein the second mode is the Full Speed mode of the USB 2.0 standard.

5. The signal reception circuit as defined in claim 1,

wherein the first signal reception circuit includes:

a first differential amplifier which outputs a differential pair of output signals amplified on the basis of the differential pair of input signals;

first and second peak hold circuits which hold peak values of the differential pair of output signals at a given node;

a first constant potential setting circuit which returns a potential of the node to a given constant potential so that the change is done slower than the potential change by holding peak values; and

a first comparison circuit which compares the node potential with the first reference level,

wherein the differential pair of input signals is detected on the basis of the comparison result by the first comparison circuit.

6. The signal reception circuit as defined in claim 5,

wherein the first and second peak hold circuits hold the lower limit value of the differential pair of output signals at a given node;

and

wherein the first constant potential setting circuit supplies the node with charges to return the node potential to a given constant potential so that the change is done slower than the potential change by the holding of the lower limit value.

7. The signal reception circuit as defined in claim 6,

wherein the first constant potential setting circuit has a constant current source which supplies small amount of charges which causes a change slower than the potential change by holding the lower limit.

8. The signal reception circuit as defined in claim 5,

wherein the first differential amplifier includes:

a first transistor of a first conductivity type having a source terminal connected to a first power source;

a second transistor of the first conductivity type having a source terminal connected to a drain terminal of the first transistor of the first conductivity type;

a third transistor of the first conductivity type having a source terminal connected to the drain terminal of the first transistor of the first conductivity type;

a first transistor of a second conductivity type having gate and drain terminals connected to a drain terminal of the second transistor of the first conductivity type, and having a source terminal connected to a second power source; and

a second transistor of the second conductivity type having gate and drain terminals connected to a drain terminal of the third transistor of the first conductivity type, and having a source terminal connected to the second power source,

wherein a given enable signal is supplied to a gate terminal of the first transistor of the first conductivity type;

wherein the differential pair of input signals is supplied to gate terminals of the second and third transistors of the first conductivity type; and

wherein the differential pair of output signals is output from the drain terminals of the first and second transistors of the second conductivity type.

9. The signal reception circuit as defined in claim 5,

wherein at least one of the first and second peak hold circuits includes:

a fourth transistor of a first conductivity type having a source terminal connected to a first power source;

a fifth transistor of the first conductivity type having a source terminal connected to a drain terminal of the fourth transistor of the first conductivity type;

a sixth transistor of the first conductivity type having a source terminal connected to the drain terminal of the fourth transistor of the first conductivity type;

a third transistor of a second conductivity type having a drain terminal connected to a drain terminal of the fifth transistor of the first conductivity type, having a gate terminal connected to a drain terminal of the sixth transistor of the first conductivity type, and having a source terminal connected to a second power source;

a fourth transistor of the second conductivity type having gate and drain terminals connected to the drain terminal of the sixth transistor of the first conductivity type, and having a source terminal connected to the second power source; and

a fifth transistor of the second conductivity type having a drain terminal connected to a gate terminal of the sixth transistor of the first conductivity type, having a gate terminal connected to the drain terminal of the third transistor of the second conductivity type, and having a source terminal connected to the second power source,

wherein a given enable signal is supplied to the a gate terminal of the fourth transistor of the first conductivity type;

wherein one of the differential pair of output signals is supplied to a gate terminal of the fifth transistor of the first conductivity type; and

wherein the node is connected to the gate terminal of the sixth transistor of the first conductivity type.

10. The signal reception circuit as defined in claim 5,

wherein the first comparison circuit includes:

a seventh transistor of a first conductivity type having a source terminal connected to a first power source;

an eighth transistor of the first conductivity type having a source terminal connected to a drain terminal of the seventh transistor of the first conductivity type;

a ninth transistor of the first conductivity type having a source terminal connected to the drain terminal of the seventh transistor of the first conductivity type;

a sixth transistor of a second conductivity type having gate and drain terminals connected to a drain terminal of the eighth transistor of the first conductivity type, and having a source terminal connected to a second power source;

a seventh transistor of the second conductivity type having a drain terminal connected to a drain terminal of the ninth transistor of the first conductivity type, having a gate terminal connected to the gate terminal of the sixth transistor of the second conductivity type, and having a source terminal connected to the second power source; and

an eighth transistor of the second conductivity type having a drain terminal connected to the gate terminal of the sixth transistor of the second conductivity type, having a gate terminal connected to the drain terminal of the seventh transistor of the second conductivity type, and having a source terminal connected to the second power source,

wherein a given enable signal is supplied to a gate terminal of the seventh transistor of the first conductivity type;

wherein the node is connected to a gate terminal of the eighth transistor of the first conductivity type;

wherein a signal of the first reference level is supplied to a gate terminal of the ninth transistor of the first conductivity type; and

wherein the comparison result is output from the drain terminal of the seventh transistor of the second conductivity type.

11. The signal reception circuit as defined in claim 10, further comprising a reference level generation circuit which includes:

a tenth transistor of the first conductivity type having a source terminal connected to the first power source;

an eleventh transistor of the first conductivity type having a source terminal connected to a drain terminal of the tenth transistor of the first conductivity type;

a twelfth transistor of the first conductivity type having a source terminal connected to the drain terminal of the tenth transistor of the first conductivity type;

a ninth transistor of the second conductivity type having gate and drain terminals connected to a drain terminal of the eleventh transistor of the first conductivity type, and having a source terminal connected to the second power source; and

a tenth transistor of the second conductivity type having gate and drain terminals connected to a drain terminal of the twelfth transistor of the first conductivity type, and having a source terminal connected to the second power source,

wherein a given enable signal is supplied to a gate terminal of the tenth transistor of the first conductivity type;

wherein a differential pair of detection level signals corresponding to the level to be detected is supplied to gate terminals of the eleventh and twelfth transistors of the first conductivity type;

wherein a signal of the first reference level is output from the drain terminal of the tenth transistor of the second conductivity type; and

wherein the reference level generation circuit has the electrical characteristics substantially equal to the first differential amplifier.

12. The signal reception circuit as defined in claim 5,

wherein the first constant current setting circuit includes:

a thirteenth transistor of a first conductivity having a source terminal connected to a first power source, and having a drain terminal connected to the node; and

a capacitor provided between the node and a second power source,

wherein a given enable signal is supplied to a gate terminal of the thirteenth transistor of the first conductivity type.

13. The signal reception circuit as defined in claim 5, further comprising an output circuit which includes:

a fourteenth transistor of a first conductivity type having a source terminal connected to a first power source; and

an eleventh transistor of a second conductivity type having a drain terminal connected to the drain terminal of the fourteenth transistor of the first conductivity type, and having a source terminal connected to a second power source,

wherein a given enable signal is supplied to a gate terminal of the fourteenth transistor of the first conductivity type;

wherein an output signal from the first comparison circuit is supplied to a gate terminal of the eleventh transistor of the second conductivity type; and

wherein a signal having a logical level corresponding to the output signal from the first comparison circuit is output from the drain terminal of the eleventh transistor of the second conductivity type.

14. The signal reception circuit as defined in claim 1,

wherein the second signal detection circuit includes:

a second differential amplifier which outputs a differential pair of output signals amplified on the basis of a differential pair of input signals;

third and fourth peak hold circuits which hold peak values of the differential pair of output signals at a given node;

a second constant potential setting circuit which returns a potential of the node to a given constant potential so that the change is done slower than the potential change by holding peak values; and

a second comparison circuit which compares the node potential with the second reference level,

wherein a differential pair of input signals is detected on the basis of the comparison result by the second comparison circuit.

15. The signal reception circuit as defined in claim 1,

wherein the differential pair of input signals is based on the Universal Series Bus standard.

18. A data transfer control device comprising:

the signal reception circuit as defined in claim 1;

and

a circuit which performs a given reception processing based on a signal detected by the signal reception circuit.

21. Electronic equipment comprising:

the data transfer control device as defined in claim 18; and

a device which performs an output, fetch or storing processing for data transferred through the data transfer control device and a bus.

16. A signal reception circuit for receiving a differential pair of input signals, comprising:

first and second reception circuits which receive a differential pair of input signals to generate first and second reception signals;

a first signal detection circuit which detects the differential pair of input signals based on a first reference level, in a first mode or the High Speed mode under the Universal Serial Bus (USB) standard 2.0;

a second signal detection circuit which detects the differential pair of input signals based on a second reference level which is higher than the first reference level, in a second mode or the Full Speed mode under the USB standard 2.0; and

a mask circuit which masks the first reception signal according to the detection result of the first signal detection circuit,

wherein the first signal reception circuit includes;

a first differential amplifier which outputs a differential pair of output signals amplified on the basis of the differential pair of input signals;

first and second peak hold circuits which hold peak values of the differential pair of output signals at a given node;

a first constant potential setting circuit which returns a potential of the node to a given constant potential so that the change is done slower than the potential change by holding peak values; and

a first comparison circuit which compares the node potential with the first reference level,

wherein the second signal detection circuit includes;

a second differential amplifier which outputs a differential pair of output signals amplified on the basis of the differential pair of input signals;

third and fourth peak hold circuits which hold peak values the differential pair of output signals at a given node;

a second constant potential setting circuit which returns a potential of the node to a given constant potential so that the change is done slower than the potential change by holding peak values; and

a second comparison circuit which compares the node potential with the second reference level,

wherein a differential pair of input signals is detected on the basis of the comparison result by the first or second comparison circuit;

wherein the first to fourth peak hold circuits hold the lower limit value of the differential pair of output signals at a given node;

wherein each of the first and second constant potential setting circuits has a constant current source which supplies small amount of charges which causes a change slower than the potential change by holding the lower limit; and

wherein a potential of the node is returned to a given constant potential by supplying the node with charges from the constant current source.

19. A data transfer control device comprising:

the signal reception circuit as defined in claim 16; and

a circuit which performs a given reception processing based on a signal detected by the signal reception circuit.

22. Electronic equipment comprising:

the data transfer control device as defined in claim 19; and

a device which performs an output, fetch or storing processing for data transferred through the data transfer control device and a bus.

17. A signal reception circuit for receiving a differential pair of input signals, comprising:

first and second reception circuits which receive a differential pair of input signals to generate first and second reception signals;

a first signal detection circuit which detects the differential pair of input signals based on a first reference level, in a first mode or the High Speed mode under the Universal Serial Bus (USB) standard 2.0;

a second signal detection circuit which detects the differential pair of input signals based on a second reference level which is higher than the first reference level, in a second mode or the Full Speed mode under the USB standard 2.0; and

a mask circuit which masks the first reception signal according to the detection result of the first signal detection circuit,

wherein the first signal reception circuit includes;

a first differential amplifier which outputs a differential pair of output signals amplified on the basis of the differential pair of input signals;

first and second peak hold circuits which hold peak values of the differential pair of output signals at a given node;

a first constant potential setting circuit which returns a potential of the node to a given constant potential so that the change is done slower than the potential change by holding peak values; and

a first comparison circuit which compares the node potential with the first reference level,

wherein the second signal detection circuit includes;

a second differential amplifier which outputs a differential pair of output signals amplified on the basis of the differential pair of input signals;

third and fourth peak hold circuits which hold peak values the differential pair of output signals at a given node;

a second constant potential setting circuit which returns a potential of the node to a given constant potential so that the change is done slower than the potential change by holding peak values; and

a second comparison circuit which compares the node potential with the second reference level,

wherein a differential pair of input signals is detected on the basis of the comparison result by the first or second comparison circuit;

wherein the first reception signal is enabled when the differential pair of input signals is detected by the first signal detection circuit;

wherein the second reception signal is enabled when the differential pair of input signals is detected based on the result of detection performed based on the result of detection performed by the second signal detection circuit.

wherein operation of the second reception circuit is controlled based on the result of detection performed by the second signal detection circuit; and

wherein the second mode shifts to the first mode, based on the second reception signal which has been enabled in the second mode.

20. A data transfer control device comprising:

the signal reception circuit as defined in claim 17; and

a circuit which performs a given reception processing based on a signal detected by the signal reception circuit.

23. Electronic equipment comprising:

the data transfer control device as defined in claim 20; and

a device which performs an output, fetch or storing processing for data transferred through the data transfer control device and a bus.