Active matrix display device and inspection method therefor

• US 20020167472A1
• Filed: 03/27/2002
• Published: 11/14/2002
• Est. Priority Date: 03/30/2001
• Status: Active Grant

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Jinno, Yushi
• Granted Patent: US 6,768,480 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

When a first transistor for switching Tr1 is ON by a gate signal, a voltage signal in accordance with a data voltage signal input to the source terminal of the first transistor Tr1 is held in a storage capacitor. A second transistor Tr2 controls an amount of current supplied to an emissive element from a power source line PVdd in accordance with the voltage signal, and a charge is accumulated in an additional capacitor C2 in accordance with the amount of current thus controlled. Defect inspection corresponding to the actual display state can be performed by examining the charge accumulated in the additional capacitor C2.

Claims

1. An active matrix display device in which each pixel comprises:

a display element;

a first transistor for switching;

a storage capacitor for holding a voltage signal supplied thereto via said first transistor, when said first transistor is ON;

a second transistor for driving an element, which supplies power from a power source line to said display element, in accordance with the voltage signal which is held by said storage capacitor and is applied to the gate of the second transistor; and

an additional capacitor which is connected such that a charge is accumulated therein as a result of a current flowing from said second transistor to said display element.

2. An active matrix display device according to claim 1, wherein

said additional capacitor is used for inspection of said active matrix display device and a matrix array substrate having said pixels formed on a substrate.

3. An active matrix display device according to claim 1, wherein

said display element is an emissive element which emits light of a brightness corresponding to the supplied power, and

said additional capacitor controls the amount of power supplied to said display element within a unit time period to thereby control the emission brightness of said display element.

4. A method of inspecting a display device according to claim 1, said method comprising the steps of:

driving each of said pixels to accumulate a charge in said additional capacitor;

measuring the amount of charge accumulated in said additional capacitor; and

inspecting the uniformity of the amount of current supplied to each display element based on the amount of charge measured for each display element.

5. An active matrix display device according to claim 1, wherein

said display element is an organic electroluminescence element including an organic emissive material as an emissive material.

6. An active matrix semiconductor device in which each cell comprises:

a cell element;

a first transistor for switching;

a storage capacitor for holding a voltage signal supplied thereto via said first transistor, when said first transistor is ON;

a second transistor for driving an element, which supplies power from a power source line to said cell element, in accordance with the voltage signal which is held by said storage capacitor and is applied to the gate of the second transistor; and

an additional capacitor which is connected such that a charge is accumulated therein as a result of a current flowing from said second transistor to said cell element.