Integrated inductance

• US 20020170743A1
• Filed: 04/05/2002
• Published: 11/21/2002
• Est. Priority Date: 04/06/2001
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Boret, Samuel
• Application Number:
  US10/117,463
• Publication Number:
  US 20020170743A1
• Time in Patent Office: Days
• US Class Current: 174/250
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An inductance device in monolithic structure is formed from a first metallization level layer of lower parallel conductive lines extending along the inductance pattern; next, on a second level, a set of vias is formed over each underlying conductive line being associated with at least two vias; and in a third metallization level, upper conductive lines interconnected to the underlying conductive lines by means of vias, the lower and upper conductive lines being shifted with respect to one another to ensure the electric continuity.

Claims

1. An inductance formed in metal layers of an integrated circuit, made of a winding wound in a plane parallel with the main surface of the integrated circuit, wherein said winding comprises:

in a first metallization level, lower parallel conductive lines extending along an inductance pattern;

in a second level, vias, each lower conductive line being associated with at least two vias; and

in a third metallization level, upper conductive lines interconnected to the lower conductive lines by means of vias, the lower and upper conductive lines being shifted with respect to one another to ensure the electric continuity.

2. A method for forming an inductance in monolithic form, including the steps of:

forming, in a first metallization level, first parallel conductive lines according to an inductance pattern;

forming, in a second metallization level, vias, so that each underlying conductive line contacts at least two vias; and

forming, in a third metallization level, second conductive lines according to the inductance pattern, the second lines being shifted with respect to the first lines to contact vias associated with distinct first lines.

3. The method of claim 2, wherein the forming of lines or vias in a given metallization level includes the steps of:

etching into an insulating layer according to the desired pattern;

depositing a layer of a conductive material to fill the previously-formed openings; and

performing a chem-mech polishing, to remove said conductive material from the upper surface of said considered insulating layer, whereby the conductive material only remains in place in the previously-formed openings.

4. The method of claim 3, wherein the conductive material is a metal.

5. The method of claim 4, wherein the conductive material is copper or a copper-based alloy.

6. An inductance device having a length of an inductance pattern in a semiconductor substrate comprising:

a plurality of first conductive lines wherein the first conductive lines are formed in the inductance pattern wherein each first conductive line is parallel to another first conductive line;

a plurality of vias wherein at least two of the vias are coupled to the first conductive line of the first plurality of conductive lines;

a plurality of second conductive lines, each second conductive line being parallel to another second conductive line and to the plurality of first conductive lines, wherein the second conductive lines, being coupled to at least two vias of the plurality of vias, are offset from and overlap the first conductive lines for the length of the inductance pattern.

7. A method of forming an inductance device having a length of an inductance pattern on a semiconductor substrate comprising the steps of:

forming a first metallization layer of a plurality of first conductive lines over a first surface of the inductance device wherein the first conductive lines are formed the inductance pattern, each first conductive line being parallel to another first conductive line

forming a plurality of vias wherein at least two vias are coupled to each of the first conductive lines;

forming a second metallization layer over a second surface wherein the plurality of vias is filled; and

forming a third metallization layer of a plurality of second conductive lines, each second conductive line being parallel to another conductive line and to the plurality of first conductive lines, wherein the second conductive lines, being coupled to at least two vias of the plurality of vias, are offset from and overlap the first conductive lines for the length of the inductance pattern.

8. A method of forming an inductance device according to claim 7 wherein the step of forming the first metallization layer includes the steps of:

removing a portion of an insulating layer wherein the removed portion is an inductance pattern;

depositing a layer of a conductive material over a surface of the inductance device to fill the removed portion of the insulating layer; and

polishing the surface of the inductance device wherein the conductive material is removed and the conductive material remains only in the removed portion of the insulating layer.

9. A method of forming an inductance device according to claim 7 wherein the step of forming the third metallization layer includes the step of:

polishing the surface of the inductance device wherein the conductive material is removed and the conductive material remains only in the plurality of vias.

10. The method of forming an inductance device according to claim 7 wherein the conductive material is a metal.

11. The method of forming an inductance device according to claim 10 wherein the conductive material is metal.

12. The method of forming an inductance device according to claim 8 wherein the step of forming the first metallization layer includes the step of:

depositing an insulating layer thus forming a surface that is substantially planar.

14. The inductance device according to claim 13 wherein the first and second conductive lines are formed of a metal.

15. The inductance device according to claim 14 wherein the first and second conductive lines are formed of copper, a copper alloy, aluminum or gold.

16. The inductance device according to claim 13 wherein each via of the plurality of vias is formed of a contact opening and a metal region.

17. The inductance device according to claim 16 wherein the via is formed of a metal.

18. The inductance device according to claim 17 wherein the via is formed of copper, a copper alloy, aluminum, tungsten or gold.

13. An inductance device having a length of an inductance pattern comprising:

a plurality of first conductive lines wherein the first conductive lines are formed in the inductance pattern wherein each first conductive line is parallel to another first conductive line for the length of the inductance pattern;

a plurality of vias wherein at least two of the vias are coupled to the first conductive line of the first plurality of conductive lines, and each via having an aspect ratio such that the via is in electrical communication with the first conductive line of the first plurality of conductive lines for the length of the inductance pattern;

a plurality of second conductive lines, each second conductive line being parallel to another second conductive line and to the plurality of first conductive lines, wherein the second conductive lines, being in electrical communication with at least two vias of the plurality of vias for the length of the inductance pattern, are offset from and overlap the first conductive lines for the length of the inductance pattern.