Si/SiGe optoelectronic integrated circuits

• US 20020171077A1
• Filed: 04/11/2002
• Published: 11/21/2002
• Est. Priority Date: 03/02/1998
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Bernd-Ulrich H. Klepser, Jack Oon Chu, Khalid Ezzeldin Ismail, Steven John Koester
• Inventors: Chu, Jack Oon, Ismail, Khalid EzzEldin, Koester, Steven John, Klepser, Bernd-Ulrich H.
• Granted Patent: US 6,784,466 B2
• Time in Patent Office: Days
• US Class Current: 257/19
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 31/0312 including, apart from doping materials or other impurities, only AIVBIV compounds, e.g. SiC
• CPC Class Codes: H01L 31/035254 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table, e.g. Si-SiGe superlattices

Abstract

An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an nor p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Claims

1. A semiconductor structure comprising a single crystal semiconductor substrate, a Si_l-xGe_x buffer layer graded from x =0 to y where y is in the range from 0.1 to 1.0, a layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m, a quantum well layer, an undoped Si_l-yGe_y spacer layer, and a doped Si_l-yGe_y supply layer, wherein said layer of relaxed Si_l-yGe_y may function as the absorbing region of a photodetector, said quantum well layer may function as the conducting channel of a field-effect transistor, and said spacer layer may function to separate dopants in said supply layer from said conducting channel.

2. The semiconductor structure of claim 1 further including spaced apart drain and source regions extending to said quantum well layer and a Schottky gate contact to control charge in said conducting channel to form a MODFET.

3. The semiconductor structure of claim 1 wherein portions of said quantum well layer, said undoped Si_l-yGe_y spacer layer and said doped Si_l-yGe_y supply layer are removed to expose said relaxed Si_l-yGe_y layer wherein electrodes are formed on said exposed relaxed Si_l-yGe_y layer to form a photodetector.

4. The semiconductor structure of claim 1 wherein said quantum well layer is under tensile strain.

5. The semiconductor structure of claim 1 wherein said quantum well layer consists of Si.

6. The semiconductor structure of claim 3 wherein said electrodes include two or more interdigitated Schottky electrodes.

7. The semiconductor structure of claim 1 wherein y is in the range from 0.2-0.35.

8. The semiconductor structure of claim 3 further including a trench extending through said exposed relaxed Si_l-yGe_y layer surface and surrounding said photodetector.

9. The semiconductor structure of claim 8 wherein said trench is filled with material including dielectric material.

10. The semiconductor structure of claim 1 further including a layer of Si over said doped Si_l-yGe_y supply layer.

11. The semiconductor structure of claim 1 wherein said doped Si_l-yGe_y supply layer is n-type.

12. The semiconductor structure of claim 6 wherein positively-biased electrodes of said photodetector provide Schottky contacts with barrier height for holes that is greater than than half the band gap of said exposed relaxed Si_l-yGe_y layer, and negatively-biased electrodes of said photodetector provide Schottky contacts with barrier height for electrons that is greater than half the band gap of said exposed relaxed Si_l-yGe_y layer.

13. The semiconductor structure of claim 6 wherein negatively-biased electrodes of said photodetector provide Schottky contacts with barrier height for electrons that is greater than half the band gap of said exposed relaxed Si_l-yGe_y layer, and positively-biased electrodes of said photodetector form Ohmic contact to an n-type doped region.

14. The semiconductor structure of claim 6 wherein negatively-biased electrodes of said photodetector form Ohmic contacts to a p-type doped region and said positively-biased electrodes of said photodetector form an Ohmic contact to an n-type doped region.

15. The semiconductor structure of claim 1 wherein said substrate is heavily-doped greater than 10¹⁸ atoms/cm³.

16. The semiconductor structure of claim 1 wherein said substrate is an SOI substrate comprising a thick Si layer, a SiO₂ layer, and a Si overlayer.

17. The semiconductor structure of claim 3 wherein said substrate is lightly-doped Si, and the region of said substrate underneath said photodetector is heavily-doped greater than 10¹⁸ atoms/cm³.

18. The semiconductor structure of claim 3 wherein said photodetector absorbing region is bordered by deep trenches extending from said photodetector surface down to said Si substrate, and filled with a dielectric material, so as to prevent photogenerated carriers generated in said Si_l-yGe_y buffer layer from diffusing lateraly past said deep trenches.

19. The semiconductor structure of claim 1 further including spaced apart drain and source regions extending to said quantum well layer, a gate dielectric layer above said supply layer between said drain and source and a gate electrode above said dielectric layer to form a MOSFET.

20. The semiconductor structure of claim I further including first and second spaced apart doped regions, one above the other, with a portion of said relaxed Si_l-yGe_y layer there between to form a photodetector and an Ohmic contact to said respective first and second doped regions for applying a potential there between.

21. The semiconductor structure of claim 20 further including a trench extending into said exposed relaxed Si_l-yGe_y layer to provide a barrier to electrical charge.

22. The semiconductor structure of claim 20 wherein said first doped region includes a region of said quantum well layer, said undoped Si_l-yGe_y spacer layer and said doped Si_l-yGe_y supply layer.

23. The semiconductor structure of claim 20 wherein said second doped region includes a region of said substrate.

25. The semiconductor structure of claim 24 further including spaced apart drain and source regions extending to said quantum well layer and a Schottky gate contact to control charge in said conducting channel to form a MODFET.

26. The semiconductor structure of claim 25 wherein portions of said p-type doped Si_l-zGe_w supply layer, said undoped Si_l-yGe_y spacer layer, said Si_l-zGe_z quantum well layer, said additional undoped Si_l-yGe_y spacer layer are removed to expose said relaxed Si_l-yGe_y layer and wherein electrodes are formed on said exposed relaxed Si_l-yGe_y layer to form a photodetector.

28. The semiconductor structure of claim 27, wherein said transistor comprises trench or mesa-defined isolation regions, source and drain electrodes and a Schottky gate contact, and said photodetector includes two or more interdigitated Schottky electrodes deposited onto the etch-exposed surface of said thin Si_l-yGe_y layer.

30. The semiconductor structure of claim 29, wherein said transistor comprises a trench or mesa-defined isolation regions, source and drain electrodes and a polysilicon or metal gate contact, and the photodetector consists of two or more Schottky electrodes formed on the surface of the top Si layer.

31. The semiconductor structure of claim 29 wherein the transistor source and drain contacts and the photodetector Schottky electrodes include one of metal-silicide and metal-germanosilicide.

24. A semiconductor structure comprising a single crystal substrate, a Si_l-xGe_x buffer layer graded from x =O to x =y, wherey is in the range from 0.1 to 0.9, a constant composition layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m, a p-type doped Si_l-wGe_w supply layer, where w <

y, an undoped Si_l-yGe_y spacer layer, a Si_l-zGe_z quantum well layer, where z >

y, and an additional undoped Si_l-yGe_y spacer layer, wherein said constant composition layer of relaxed Si_l-yGe_y may function as the absorbing region of a photodetector, and said Si_l-zGe_z quantum well layer may function as the conducting channel of a field-effect transistor.

27. A semiconductor structure comprising a single crystal semiconductor substrate, a Si_l-xGe_x buffer layer graded from x =O to y in the range from 0.1 to 0.9, followed by a plurality of layers forming a symmetrically-strained superlattice and consisting of alternating layers of Si_l-wGe_w and Si_l-zGe_z, where w <

y <

z, and having corresponding individual thicknesses such that the average Ge-composition of the layer is y, and having a total thickness in the range from 0.25 μ

m to 10 μ

m, and additionally a thin Si_l-yGe_y layer, a quantum well layer, an undoped Si_l-yGe_y spacer layer, and an n-type doped Si_l-yGe_y supply layer, wherein said symmetric superlattice may function as the absorbing region of a photodetector, and said quantum well layer may function as the conducting channel of a field-effect transistor.

29. A semiconductor structure comprising a substrate selected from the group consisting of Si and SOI, a Si_l-xGe_x buffer layer graded from x =O to x =y, where y is in the range from 0.1 to 1.0, a constant composition layer of relaxed Si_l-yGe_y, of thickness 0.25 μ

m to 10 μ

m a thin Si surface layer, and a thin gate dielectric, wherein said constant composition layer of relaxed Si_l-yGe_y acts as the absorbing region of a photodetector, and said Si surface layer acts as the conducting channel of a field-effect transistor.

32. A semiconductor structure comprising a single crystal semiconductor substrate, a Si_l-xGe_x buffer layer graded from x =O to y where y is in the range from 0.1 to 0.9, a layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m, an n-type doped Si_l-yGe_y supply layer, a first undoped Si_l-yGe_y layer, a second undoped Si_l-yGe_y offset layer, a second quantum well layer, a third undoped Si_l-yGe_y offset layer, an undoped Si layer, a gate dielectric and a gate electrode layer wherein said layer of relaxed Si_l-yGe_y may function as the absorbing region of a photodetector, and said first quantum well layer may act as an electron channel for an n-MOSFET, and said second quantum well layer acts as a hole channel for a p-MOS FET.

33. The semiconductor structure of claim 32 wherein said n-MOSFET comprises trench or mesa-defined isolation regions, spaced apart source and drain regions extending to said first quantum well layer and a first gate electrode to control charge in said first quantum well layer, and said p-MOSFET comprises trench or mesa-defined isolation regions, spaced apart source and drain regions extending to said second quantum well layer and a second gate electrode to control charge in said second quantum well layer.

34. The semiconductor structure of claim 33 wherein portions of said n-type doped Si_l-yGe_y supply layer, said first undoped Si_l-yGe_y layer, said second undoped Si_l-yGe_y offset layer, said second quantum well layer, said third undoped Si_l-yGe_y offset layer, said undoped Si layer, said gate dielectric layer and said gate electrode layer are removed to expose said relaxed Si_l-yGe_y layer wherein electrodes are formed on said exposed relaxed Si_l-yGe_y layer to form a photodetector.

36. The method of claim 35 further including the steps of forming spaced apart drain and source regions extending to said quantum well layer and forming a Schottky gate contact to control charge in said conducting channel to form a MODFET.

37. The method of claim 35 further including the steps of removing portions of said quantum well layer, said undoped Si_l-yGe_y spacer layer and said doped Si_l-yGe_y supply layer to expose said relaxed Si_l-yGe_y layer and forming electrodes on said exposed relaxed Si_l-yGe_y layer to form a photodetector.

38. The method of claim 37 further including the step of forming a trench extending into said exposed relaxed Si_l-yGe_y layer to provide a barrier to electrical charge.

39. The method of claim 37 further including the step of doping said substrate underneath said photodetector greater than 10¹⁸ atoms/cm³.

40. The method of claim 35 further including the steps of forming spaced apart drain and source regions extending to said quantum well layer, forming a gate dielectric layer above said supply layer between said drain and source and forming a gate electrode above said dielectric layer to form a MOSFET.

41. The method of claim 35 further including the steps of forming first and second spaced apart doped regions, one above the other with a portion of said relaxed Si_l-yGe_y layer there between to form a photodetector and forming an Ohmic contact to said respective first and second doped regions for applying a potential therebetween.

42. The method of claim 41 further including the step of forming a trench extending through said exposed relaxed Si_l-yGe_y layer to provide a barrier to electrical charge.

43. The method of claim 41 wherein said step of forming said second doped region includes the step of doping said substrate.

35. A method for forming a semiconductor structure comprising the steps of:

selecting a single crystal semiconductor substrate,

forming a Si_l-xGe_x buffer layer graded from x =O to y in the range from 0.1 to 1.0, forming a layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m forming a quantum well layer,

forming an undoped Si_l-yGe_y spacer layer, and forming a doped Si_l-yGe_y supply layer.

44. A method of forming a semiconductor structure comprising the steps of:

selecting a single crystal substrate,

forming a Si_l-xGe_x buffer layer graded from x =O to x =y where y is in the range from 0.1 to 0.9,

forming a constant composition layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m,

forming a p-type doped Si_l-zGe_z supply layer, where w is greater than y,

forming an undoped Si_l-yGe_y spacer layer,

forming a Si_l-zGe_z quantum well layer, where z is greater than y, and

forming an additional undoped Si_l-yGe_y spacer layer, wherein said constant composition layer of relaxed Si_l-yGe_y may function as the absorbing region of a photodetector, and said Si_l-zGe_z quantum well layer may function as the conducting channel of a field effect transistor.

45. The method of claim 44 further including the step of forming spaced apart drain and source regions extending to said, quantum well layer and a forming a Schottky contact to control charge in said conducting channel to form a MODFET.

46. The method of claim 44 further including the steps of removing portions of said p-type doped Si_l-wGe_w supply layer, said undoped Si_l-yGe_y spacer layer, said Si_l-zGe_z quantum well layer, said additional undoped Si_l-yGe_y spacer layer to expose said relaxed Si_l-yGe_y layer and forming electrodes on said exposed relaxed Si_l-yGe_y layer to form a photodetector.

48. The method of claim 47 further including the steps of forming a trench or mesa defined isolation regions,

forming source and drain electrodes and a Schottky gate contact, and

forming two or more interdigitated Schottky electrodes deposited onto the etch exposed surface of Si_l-yGe_y buffer layer.

50. The method of claim 49 further including the step of forming a trench or mesa defined isolation regions,

forming source and drain electrodes and a gate electrode, and

forming two or more Schottky electrodes on the surface of the top Si layer to form a photodetector.

51. The method of claim 49 wherein said steps of forming said transistor source and drain electrodes and the photodetector Schottky electrodes include the step of forming one of a metal silicide and a metal germanosilicide.

47. A method for forming a semiconductor structure comprising the steps of:

selecting a single crystal semiconductor substrate,

forming a Si_l-xGe_x buffer layer graded from x =O to x =y where y is in the range from 0.1 to 0.9,

forming a symmetrically strained superlattice and comprising alternating layers of Si_l-wGe_w and Si_l-zGe_z, where w is greater thany and where y is greater than z, said alternating layers having corresponding individual thicknesses such that the average Ge composition of the layer is y, said alternating layers having a total thickness in the range from 0.25 μ

m to 10 μ

m,

forming an additionally thin Si_l-yGe_y layer,

forming a quantum well layer,

forming an undoped Si_l-yGe_y spacer layer,

formining an n-type doped Si_l-zGe_z supply layer, wherein said symmetrically strained superlattice may function as the absorbing region of a photodetector, and said quantum well layer may function as the conducting channel of a field effect transistor.

49. A method for forming a semiconductor structure comprising the steps of:

selecting a substrate from the group consisting of Si, SiGe, Ge, GaAs, SiC, SOS, and SOI,

forming a Si_l-xGe_x buffer layer graded from x =O to x =y, where y is in the range from 0.1 to 1.0,

forming a constant composition layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m,

forming a thin Si surface layer,

forming a thin gate dielectric,

wherein said constant composition layer of relaxed Si_l-yGe_y acts as the absorbing region of a photodetector, and said Si surface layer acts as the conducting channel of a field effect transistor.

52. A method for forming a semiconductor structure comprising the steps of forming a single crystal semiconductor substrate, forming a Si_l-xGe_x buffer layer graded from x =O to y where y is in the range from 0.1 to 0.9, forming a layer of relaxed Si_l-yGe_y having a thickness in the range from 0.25 μ

m to 10 μ

m, forming an n-type doped Si_l-yGe_y supply layer, forming a first undoped Si_l-yGe_y layer, forming a first quantum well layer which acts as an electron channel for an NMOS FET, forming a second undoped Si_l-yGe_y offset layer, forming a second quantum well layer which acts as a hole channel for a PMOS FET, forming a third undoped Si_l-yGe_y offset layer, forming an undoped Si layer, forming a gate dielectric and foming a gate electrode layer whereby NMOS FET'"'"'s and PMOS FET'"'"'s may be formed by forming the respective n-type and p-type drain and source regions.