Dc testing apparatus and semiconductor testing apparatus

• US 20020171448A1
• Filed: 04/26/2002
• Published: 11/21/2002
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Takeuchi, Hideo
• Granted Patent: US 6,683,470 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

The apparatus of the present invention includes: a sequencer 11 for outputting a start signal, a timing signal, a write-in signal, and a clock signal sequentially, when an AD start signal is input; an ADC 12 for measuring an output of a device under test (DUT) 3 to which a test pattern is input, when the start signal is input; an arithmetic/logical unit (ALU) 13 for outputting an output voltage value of the ADC when the timing signal is input, and for outputting a result of comparing the output voltage value with an expected value to the pattern generator as a PASS/FAIL signal; an address counter 14 for updating an address value to be output when the clock signal is input; and a history memory for storing a measurement value in an address indicated by the address value when the write-in signal is input. This configuration makes it possible to measure each voltage value output from the DUT for a test pattern corresponding each AD start signal.

Claims

1. A DC testing apparatus comprising:

a sequencer for outputting a start signal, a timing signal, a write-in signal, and a clock signal sequentially, when an AD start signal for each test pattern is input from a pattern generator for generating the test pattern to be input to a device under test (DUT);

an analog/digital converter for measuring an output of said DUT to which the test pattern is input, when said start signal is input;

an arithmetic/logical unit (ALU) for outputting an output voltage value of said analog/digital converter as a measurement value, when said timing signal is input, and for outputting a result of comparing said output voltage value with an expected value to said pattern generator as a PASS/FAIL signal;

an address counter for updating an address value to be output, when said clock signal is input; and

a history memory for storing said measurement value in an address indicated by said address value, when said write-in signal is input.

2. The DC testing apparatus according to claim 1, wherein said history memory comprises a memory apparatus that stores each measurement value obtained through a plurality of measurements by inputting one said AD start signal.

3. A semiconductor testing apparatus equipped with a DC testing apparatus, wherein:

said DC testing apparatus comprises;

a pattern generator for generating a test pattern to be input to a device under test, and for outputting an AD start signal for each test pattern;

a sequencer for outputting a start signal, a timing signal, a write-in signal, and a clock signal sequentially, when said AD start signal is input;

an analog/digital converter for measuring an output of said DUT to which the test pattern is input, when said start signal is input;

an arithmetic/logical unit for outputting an output voltage value of said analog/digital converter as a measurement value, when said timing signal is input, and for outputting a result of comparing the output voltage value with an expected value to said pattern generator as a PASS/FAIL signal;

an address counter for updating an address value to be output, when said clock signal is input; and

a history memory for storing the measurement value in an address indicated by said address value, when said write-in signal is input.