High gain, high bandwidth, fully differential amplifier

• US 20020171486A1
• Filed: 03/27/2001
• Published: 11/21/2002
• Est. Priority Date: 03/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Krupnik, Yoel
• Granted Patent: US 6,525,608 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45028 the differential amplifier amplifying transistors are folded cascode coupled transistors
• CPC Class Codes: H03F 2203/45292 the AAC comprising biasing means controlled by the signal
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45654 Controlling the active amplifying circuit of the differential amplifier

Abstract

A high gain, high bandwidth, fully differential CMOS amplifier.

Claims

1. An amplifier comprising:

a first differential pair comprising first and second transistors;

a first cascode transistor coupled to the first transistor of the first differential pair to form a folded-cascode pair, the first cascode transistor having a first terminal and a second terminal;

a first current mirror comprising first and second transistors to bias currents in the first and second transistors of the first differential pair, wherein the first transistor of the first current mirror is coupled to bias current in the first cascode transistor; and

a first auxiliary amplifier to provide negative feedback from the first terminal of the first cascode transistor to the second terminal of the first cascode transistor.

2. The amplifier as set forth in claim 1, wherein

the first and second transistors of the first differential pair are field effect transistors having a first carrier type;

the first and second transistors of the first current mirror are field effect transistors having a second carrier type complementary to the first carrier type; and

the first cascode transistor is a field effect transistor wherein the first terminal comprises a source and the second terminal comprises a gate.

3. The amplifier as set forth in claim 2, wherein the first auxiliary amplifier comprises:

a first field effect transistor having the second carrier type, having a gate connected to the source of the first cascode transistor, and having a drain; and

a second field effect transistor having the second carrier type, having a source connected to the drain of the first field effect transistor of the first auxiliary amplifier, and a drain connected to the gate of the first cascode transistor.

4. The amplifier as set forth in claim 1, further comprising:

a second differential pair comprising first and second transistors;

a second cascode transistor coupled to the first transistor of the second differential pair to form a folded-cascode pair, the second cascode transistor having a first terminal and a second terminal; and

a second current mirror comprising first and second transistors to bias currents in the first and second transistors of the second differential pair, wherein the first transistor of the second current mirror is coupled to bias current in the second cascode transistor;

wherein the first auxiliary amplifier is coupled to provide negative feedback from the first terminal of the second cascode transistor to the second terminal of the second cascode transistor.

5. The amplifier as set forth in claim 4, further comprising:

a third cascode transistor coupled to the second transistor of the first differential pair to form a folded-cascode pair, the third cascode transistor having a first terminal and a second terminal;

a fourth cascode transistor coupled to the second transistor of the second differential pair to form a folded-cascode pair, the fourth cascode transistor having a first terminal and a second terminal; and

a second auxiliary amplifier to provide negative feedback from the first terminal of the third cascode transistor to the second terminal of the third cascode transistor, and to provide negative feedback from the first terminal of the fourth cascode transistor to the second terminal of the fourth cascode transistor.

6. The amplifier as set forth in claim 5, wherein the second terminals of the first and second cascode transistors are at a same potential and the second terminals of the third and fourth cascode transistors are at a same potential.

7. The amplifier as set forth in claim 5, wherein

the first and second transistors of the first differential pair, the first and second transistors of the second current mirror, and the second and fourth cascode transistors are each field effect transistors having a first carrier type, a source, a gate, and a drain;

and

the first and second transistors of the second differential pair, the first and second transistors of the first current mirror, and the first and third cascode transistors are each field effect transistors having a second carrier type complementary to the first carrier type, a source, a gate, and a drain;

wherein the first terminals of the first, second, third, and fourth cascode transistors each comprise their respective sources; and

the second terminals of the first, second, third, and fourth cascode transistors each comprise their respective gates.

8. An amplifier to provide a first output voltage indicative of a differential of first and second input voltages, the operational amplifier comprising:

a first input node at the first input voltage;

a second input node at the second input voltage;

a first output node at the first output voltage;

a first differential pair comprising first and second transistors;

a first cascode transistor coupled to the first transistor of the first differential pair to form a folded-cascode pair;

a second differential pair comprising first and second transistors;

wherein the first transistors of the first and second differential pairs are coupled to the first input node to be responsive to the first input voltage, and the second transistors of the first and second differential pair are coupled to the second input node to be responsive to the second input voltage;

a second cascode transistor coupled to the first transistor of the second differential pair to form a folded-cascode pair;

a first current mirror comprising first and second transistors to sink, respectively, current from the first and second transistors of the first differential pair, wherein the first transistor of the first current mirror is coupled to sink current from the first cascode transistor;

a second current mirror comprising first and second transistors to source, respectively, current to the first and second transistors of the second differential pair,

wherein the first transistor of the second current mirror is coupled to source current to the second cascode transistor; and

a first auxiliary amplifier to control current flow in the first cascode transistor by negative feedback, and to control current flow in the second cascode transistor by negative feedback;

wherein the first and second cascode transistors are coupled to the first output node to provide the first output voltage.

9. The amplifier as set forth in claim 8, the amplifier further providing a second output voltage indicative of the differential of the first and second input voltages, the amplifier further comprising:

a second output node at the second output voltage;

a third cascode transistor coupled to the second transistor of the first differential pair to form a folded-cascode pair;

a fourth cascode transistor coupled to the second transistor of the second differential pair to form a folded-cascode pair; and

a second auxiliary amplifier to control current flow in the third cascode transistor by negative feedback, and to control current flow in the fourth cascode transistor by negative feedback;

wherein the third and fourth cascode transistors are coupled to the second output node to provide the second output voltage.

10. The operational amplifier as set forth in claim 9, wherein

the first and second transistors of the first differential pair, the second and fourth cascode transistors, and the first and second transistors of the second current mirror are pFETs;

and

the first and second transistors of the second differential pair, the first and third cascode transistors and the first and second transistors of the first current mirror are nFETs;

wherein the first and second cascode transistors have gates having a same potential, and the third and fourth cascode transistors have gates having a same potential.

11. An amplifier comprising:

a first differential pair comprising first and second unipolar transistors of a first carrier type, each having a drain, a gate, and a source;

a first cascode unipolar transistor of a second carrier type complementary to the first carrier type, having a gate, having a drain, and having a source connected to the drain of first transistor of the first differential pair;

a first current mirror comprising first and second unipolar transistors of the second carrier type, each having a gate, a drain, and a source, wherein the drain of the first transistor of the first current mirror is connected to the drain of the first transistor of the first differential pair, and wherein the drain of the second transistor of the first current mirror is connected to the drain of the second transistor of the first differential pair;

a second differential pair comprising first and second unipolar transistors of the second carrier type, each having a drain, a gate, and a source;

a second cascode unipolar transistor of the first carrier type, having a gate, having a drain, and having a source connected to the drain of first transistor of the second differential pair;

a second current mirror comprising first and second unipolar transistors of the first carrier type, each having a gate, a drain, and a source, wherein the drain of the first transistor of the second current mirror is connected to the drain of the first transistor of the second differential pair, and wherein the drain of the second transistor of the second current mirror is connected to the drain of the second transistor of the second differential pair;

a third cascode unipolar transistor of the second carrier type, having a gate, having a drain, and having a source connected to the drain of second transistor of the first differential pair;

a fourth cascode unipolar transistor of the first carrier type, having a gate, having a drain, and having a source connected to the drain of second transistor of the second differential pair;

a first auxiliary amplifier to provide feedback from the source of the first cascode transistor to the gate of the first cascode transistor, and to provide feedback from the source of the second cascode transistor to the gate of the second cascode transistor; and

a second auxiliary amplifier to provide feedback from the source of the third cascode transistor to the gate of the third cascode transistor, and to provide feedback from the source of the fourth cascode transistor to the gate of the fourth cascode transistor.

12. The amplifier as set forth in claim 11, the first auxiliary amplifier comprising:

a first unipolar transistor of the second carrier type having a gate connected to the source of the first cascode transistor, and having a drain;

a second unipolar transistor of the second carrier type having a source connected to the drain of the first transistor of the first auxiliary amplifier, and having a drain connected to the gate of the first cascode transistor;

a third unipolar transistor of the first carrier type having a gate connected to the source of the second cascode transistor, and having a drain; and

a fourth unipolar transistor of the first carrier type having a source connected to the drain of the third transistor of the first auxiliary amplifier, and having a drain connected to the gate of the second cascode transistor and to the drain of the second transistor of the first auxiliary amplifier.

14. The amplifier as set forth in claim 13, wherein

the first and second cascode transistors are field effect transistors each having a drain, source, and gate, wherein the gates of the first and second cascode transistors are connected to each other and the drains of the first and second cascode transistors are connected to each other;

the third and fourth cascode transistors are field effect transistors each having a drain, source, and gate, wherein the gates of the third and fourth cascode transistors are connected to each other and the drains of the third and fourth cascode transistors are connected to each other;

wherein the first auxiliary amplifier is connected to the first and second cascode transistors to provide negative feedback from the source of the first cascode transistor to the gate of the first cascode transistor and to provide negative feedback from the source of the second cascode transistor to the gate of the second cascode transistor; and

wherein the second auxiliary amplifier is connected to the third and fourth cascode transistors to provide negative feedback from the source of the third cascode transistor to the gate of the third cascode transistor and to provide negative feedback from the source of the fourth cascode transistor to the gate of the fourth cascode transistor.

15. The amplifier as set forth in claim 14, wherein the first auxiliary amplifier comprises:

a first field effect transistor having a gate connected to the source of the first cascode transistor, and having a drain;

a second field effect transistor having a source connected to the drain of the first transistor of the first auxiliary amplifier and having a drain connected to the gate of the first code transistor;

a third field effect transistor having a gate connected to the source of the second cascose transistor, and having a drain; and

a fourth field effect transistor having a source connected to the drain of the third transistor of the first auxiliary amplifier and having a drain connected to the gate of the second cascode transistor and to the drain of the first transistor of the first auxiliary amplifier.

13. An amplifier comprising:

a first differential pair;

a first current mirror to sink current from the first differential pair;

a second differential pair;

a second current mirror to source current to the second differential pair;

a first cascode transistor connected to the first differential pair;

a second cascode transistor connected to the second differential pair;

a third cascode transistor connected to the first differential pair;

a fourth cascode transistor connected to the second differential pair;

a first auxiliary amplifier to provide feedback to control current in the first and second cascode transistors; and

a second auxiliary amplifier to provide feedback to control current in the third and fourth cascode transistors.