Method for tuning an antenna resonant circuit of a passive transponder

• US 20020171602A1
• Filed: 05/13/2002
• Published: 11/21/2002
• Est. Priority Date: 05/18/2001
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Friedrich, Ulrich, Feibig, Cordula
• Granted Patent: US 6,952,560 B2
• Time in Patent Office: Days
• US Class Current: 343/907
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/0726 the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card

Abstract

In the previously known methods for tuning the antenna resonant circuit, in the case of passive transponders, their range in a high-frequency carrier field is generally limited to a few cm as the supply voltage for the integrated circuit gained from the carrier field falls very quickly with increasing distance.

According to the new method, the range of passive transponders in a high-frequency electromagnetic carrier field is substantially increased, in that the real and imaginary parts connected to the contact surface of the antenna contact are minimized and the energy absorbed from the carrier field by means of a serial resonant circuit is used to the greatest possible extent for generating the supply voltage for the integrated circuit of the transponder.

Claims

1. Method for tuning an antenna resonant circuit of a passive transponder, the operating energy of which is capacitively drawn from a high-frequency electromagnetic carrier field, and

which has a semiconductor body with an integrated circuit (IS) with a signal part (ST) with reference potential connection,

which has an antenna arrangement arranged on a substrate,

the antenna arrangement is linked to the integrated circuit (IS) via a contact surface (BP) connected on the semiconductor body,

in which the antenna (AN) forms a serial resonant circuit with the input capacitor of the integrated circuit (IS),

wherein

the parasitic, capacitive and resistive parts, which form a current path between the contact surface (BP) and the reference potential, are reduced in order to raise the quality of the antenna resonant circuit.

2. Method according to claim 1, wherein the current path is divided into a first current path and a second current path at at least one point by means of a series connection and a parallel connection of capacitive and resistive parts.

3. Method according to claim 2, wherein a parallel connection of a low capacitance of low quality, the value of which preferably lies in the range of a few fF, and a parallel connection of a low capacitance of high quality, the value of which preferably lies in the range of a few fF, is switched in series to a first capacitance of high quality.

4. Method according to claim 3, wherein the low capacitances are generated by means of diodes.

5. Method according to claim 3, wherein a conductive layer (ALB2), which together with the contact surface (BP) forms a capacitor with high quality, is implanted in an insulating layer (ISO) lying under the contact surface (BP).

6. Semiconductor arrangement for implementing the method according to the invention according to one of the claims 1 to 5 with a first conductive layer (ALB1) as contact surface (BP) for connecting an antenna (AN) to an integrated circuit (IS), an insulating layer (ISO), a first zone (D1) of a first conductivity type, a second zone (D2) of a second conductivity type, and a third highly doped zone (D2P) of the second conductivity type, which links a contact (ALK), which has a reference potential, to the semiconductor substrate,

wherein

another conductive layer (ALB2), the lateral extent of which is greater than the extent of the layer (ALB1), is arranged within the insulating layer (ISO), and

the layer (ALB2) has a connection to the first zone (D1) in order to form a Schottky diode, and

the first zone (D1) surrounds the third zone (D2P).

7. Semiconductor arrangement according to claim 6,

wherein

a fourth zone (D2PP) of the second conductivity type, which is surrounded by the first zone (D1), is arranged under the connector area of the layer (ALB2).