Embedded electrically programmable read only memory devices

• US 20020173101A1
• Filed: 04/23/2002
• Published: 11/21/2002
• Est. Priority Date: 01/11/2000
• Status: Active Grant

• Current Assignee: Jeng-Jye Shau
• Original Assignee: Jeng-Jye Shau
• Inventors: Shau, Jeng-Jye
• Granted Patent: US 6,756,645 B2
• Time in Patent Office: Days
• US Class Current: 438/264
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention teaches novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. They can be manufactured by dynamic random access memory (DRAM) technologies, standard logic technologies, or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for DRAM, the programmable firmware for logic products, and the security identification circuits for IC products.

Claims

1. A method for manufacturing a plurality of electrically programmable read only memory (EPROM) cells and a plurality of dynamic random access memory (DRAM) on a single wafer comprising:

forming a plurality of semiconductor transistors near a top surface of said single wafer; and

simultaneously forming a coupling capacitor for each of said EPROM cells and a storage capacitor for each of said DRAM cells with said coupling capacitor and said storage capacitor having a substantially identical shape and structure disposed immediately above said semiconductor transistors.

2. The method of claim 1 wherein:

said step of forming said semiconductor transistors of said EPROM cells further includes a step of forming a gate for each of said transistors for functioning as a floating gate for each of said EPROM cells.

3. The method of claim 1 wherein:

said step of forming said semiconductor transistors of said EPROM cells further includes step of forming a drain and a source for connecting to an EPROM bitline (EBL) and a ground voltage.

4. The method of claim 1 wherein:

said step of forming said storage capacitor of said EPROM cells further includes a step of forming an electrode for functioning as a control gate for each of said EPROM cells.

11. The method of claim 2 wherein:

said step of forming said stress means is a step of forming a means for applying a high voltage to said active circuit elements.

13. The EPROM device of claim 12 further comprising:

a sensing means to sense a change of a current versus voltage variation (Δ

i/Δ

v) performance characteristic of said active circuit elements.

14. The EPROM device of claim 12 wherein:

said active circuit elements are MOS transistors.

15. The EPROM device of claim 12 wherein:

said active circuit elements are bipolar transistors.

16. The EPROM device of claim 12 wherein:

said active circuit elements are diodes.

17. The EPROM device of claim 12 wherein:

said stress means is provided to cause hot carrier stress to said active circuit elements.

18. The EPROM device of claim 11 wherein:

said stress means is provided to apply high voltage to said active circuit elements.

20. The single semiconductor wafer of claim 19 wherein:

each of said semiconductor transistors of said EPROM cells further includes a gate for functioning as a floating gate for each of said EPROM cells.

21. The single semiconductor wafer of claim 19 wherein:

each of said semiconductor transistors of said EPROM cells further includes a drain and a source for connecting to an EPROM bitline (EBL) and a a ground voltage.

22. The single semiconductor wafer of claim 19 wherein:

each of said storage capacitor of said EPROM cells further includes an electrode for functioning as a control gate for each of said EPROM cells.

5. A method for manufacturing a EPROM device comprises

forming a plurality of active circuit elements;

and

forming a stress means to apply electrical stresses to change an active performance characteristic of said active circuit elements.

6. The method of claim 5 further comprising:

forming a sensing means to sense a change of said active performance characteristic of said active circuit elements.

7. The method of claim 5 wherein:

said step of forming said active circuit elements is a step of forming a plurality of MOS transistors.

8. The method of claim 5 wherein:

said step of forming said active circuit elements is a step of forming a plurality of bipolar transistors.

9. The method of claim 5 wherein:

said step of forming said active circuit elements is a step of forming a plurality of diodes.

10. The method of claim 5 wherein:

said step of forming said stress means is a step of forming a means for causing hot carrier stress to said active circuit elements.

12. An EPROM device comprises

a plurality of active circuit elements;

and

a stress means to apply electrical stresses to change an active performance characteristic of said active circuit elements.

19. A single semiconductor wafer supports a plurality of electrically programmable read only memory (EPROM) cells and a plurality of dynamic random access memory (DRAM) wherein:

each of said EPROM cells includes a coupling capacitor and each of said DRAM cells includes a storage capacitor wherein said coupling capacitor and said storage capacitor having a substantially identical shape and structure disposed immediately above a plurality of semiconductor transistors disposed at a top surface of said wafer whereby said EPROM cell and said DRAM cells are simultaneously manufactured on said single semiconductor wafer.