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Aircraft location and tracking system

  • US 20020173888A1
  • Filed: 01/07/2002
  • Published: 11/21/2002
  • Est. Priority Date: 05/21/2001
  • Status: Abandoned Application
First Claim
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1. An integrated flight apparatus for networking a flight data recorder or data collection system to a multifunctional GPS receiver and satellite communication tracking device comprising:

  • An integrated microprocessor incorporating on board RAM (Random Access Memory), buffers and EEPROM (Electrically erasable programmable read-only memory). The processor or CPU (Central Processing Unit) is attached to the circuit board via the data and system busses. These circuits connect every component on the circuit board providing bi-directional communication between component devices. The CPU is responsible for processing data from the satellite transceiver, GPS receiver, LCD (Liquid Crystal Display) screen and any other data that can be inputted and outputted through the serial ports;

    Multiple serial ports (Four) with alternate protocol specifications such as RS-232 and Parallel/SCSI (Small Computer Serial Interface). The serial ports that are attached to the processor via the circuit board for data and signal exchange;

    ROM (Read-only memory) microchips are linked to the processor via the system and data bus that provides operational system pre-programmed functions and calculations;

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