System on a chip for packet processing

• US 20020174255A1
• Filed: 07/25/2002
• Published: 11/21/2002
• Est. Priority Date: 05/18/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hayter, Mark D., Desai, Shailendra S., Chui, Kwong-Tak A.
• Granted Patent: US 7,320,022 B2
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload

Abstract

A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller'"'"'s input queue is approaching fullness.

Claims

1. An apparatus comprising:

a processor coupled to an interconnect;

a cache coupled to the interconnect;

a memory controller coupled to the interconnect; and

a packet interface circuit for receiving packets from a packet interface and causing the packets to be transmitted on the interconnect for storage;

wherein the processor, the cache, the memory controller, and the packet interface circuit are integrated into a single semiconductor substrate and wherein the processor is programmable to process the packets received by the packet interface.

2. The apparatus as recited in claim 1 wherein the packet interface circuit, in response to receiving a packet from the packet interface, is configured to cause a first portion of the packet to be stored in the cache and a remaining portion of the packet to be stored in a memory to which the memory controller is coupled.

3. The apparatus as recited in claim 2 wherein the first portion includes at least a portion of a header of the packet.

4. The apparatus as recited in claim 2 wherein the first portion of the packet is transmitted on the interconnect as one or more transactions, and wherein the one or more transactions each include an indication that a block transmitted via the transaction is to be stored in the cache.

5. The apparatus as recited in claim 4 wherein the interconnect comprises a bus, and wherein the indication is a signal during the address phase of each of the one or more transactions on the bus.

6. The apparatus as recited in claim 2 wherein the packet interface comprises an Ethernet media access controller.

7. The apparatus as recited in claim 2 wherein the packet interface circuit includes a configuration register programmable to store a size of the first portion of the packet.

8. The apparatus as recited in claim 1 wherein the memory controller is coupled to provide a first block signal for the packet interface circuit and a second block signal for other devices coupled to the interconnect, and wherein memory transactions from the packet interface circuit are inhibited from initiation on the interconnect in response to an assertion of the first block signal, and wherein the other devices are configured to inhibit initiating memory transactions on the interconnect in response to an assertion of the second block signal.

9. The apparatus as recited in claim 8 wherein the memory controller comprises an input queue having a plurality of entries for transactions, and wherein the memory controller is configured to assert the second block signal responsive to a number of the plurality of entries which are available being less than a first number.

10. The apparatus as recited in claim 9 wherein the memory controller is further configured to assert the first block signal in response to the number of the plurality of entries which are available being less than a second number, the second number being less than the first number.

11. The apparatus as recited in claim 9 wherein the memory controller comprises a configuration register programmable to store and indication of the first number.

12. The apparatus as recited in claim 1 wherein the packet interface circuit is coupled to the interconnect through a bus bridge.

14. The method as recited in claim 13 further comprising:

storing a first portion of the packet in the cache; and

storing a remaining portion of the packet in a memory to which the memory controller is coupled.

15. The method as recited in claim 14 wherein the first portion includes at least a portion of a header of the packet.

16. The method as recited in claim 14 wherein transmitting comprises transmitting the first portion of the packet on the interconnect as one or more transactions, and wherein the one or more transactions each include an indication that a block transmitted via the transaction is to be stored in the cache.

17. The method as recited in claim 13 further comprising:

the memory controller providing a first block signal for the packet interface circuit and a second block signal for other devices coupled to the interconnect;

inhibiting initiating memory transactions on the interconnect from the packet interface circuit in response to an assertion of the first block signal; and

the other devices inhibiting initiating memory transactions on the interconnect in response to an assertion of the second block indication.

18. The method as recited in claim 17 further comprising the memory controller asserting the second block signal responsive to a number of a plurality of entries in an input queue of the memory controller which are available being less than a first number.

19. The method as recited in claim 18 further comprising the memory controller asserting the first block signal in response to the number of the plurality of entries which are available being less than a second number, the second number being less than the first number.

13. A method comprising:

receiving a packet from a packet interface in a packet interface circuit; and

transmitting the packet for storage on an interconnect to which a cache, a memory controller, and a processor are coupled;

wherein the processor, the cache, the memory controller, and the packet interface circuit are integrated into a single semiconductor substrate.