Power semiconductor devices having retrograded-doped transition regions that enhance breakdown voltage characteristics and methods of forming same

• US 20020175351A1
• Filed: 04/11/2001
• Published: 11/28/2002
• Est. Priority Date: 04/11/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Granted Patent: US 6,781,194 B2
• Time in Patent Office: Days
• US Class Current: 257/242
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

A power field effect transistor utilizes a retrograded-doped transition region to enhance forward on-state and reverse breakdown voltage characteristics. Highly doped shielding regions may also be provided that extend adjacent the transition region and contribute to depletion of the transition region during both forward on-state conduction and reverse blocking modes of operation. In a vertical embodiment, the transition region has a peak first conductivity type dopant concentration at a first depth relative to a surface on which gate electrodes are formed. A product of the peak dopant concentration and a width of the transition region at the first depth is preferably in a range between 1×10¹² cm⁻² and 7×10¹² cm⁻².

Claims

1. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region; and

a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to the surface.

2. The device of claim 1, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

3. The device of claim 1, wherein said first and second insulated electrodes are electrically connected to said first and second source regions.

4. The device of claim 1, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

5. The device of claim 1, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

6. The device of claim 1, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of the non-rectifying junction is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

7. The device of claim 1, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region, a width of said transition region at the first depth and a width of the mesa is less than 2×

10¹⁵ cm<sup>−

1</sup>.

8. The device of claim 1, wherein said first source region and said first base region are self-aligned to said insulated gate electrode.

9. The device of claim 1, further comprising:

a first shielding region of second conductivity type that extends between said first base region and the drift region and is more highly doped than said first base region; and

a second shielding region of second conductivity type that extends between said second base region and the drift region and is more highly doped than said second base region.

10. The device of claim 9, wherein said first and second shielding regions form respective P-N rectifying junctions with said transition region;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width between said first and second shielding regions is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10² cm<sup>−

2</sup>.

11. The device of claim 1, wherein the drift region has a vertically retrograded first conductivity type doping profile therein relative to the surface.

12. The device of claim 1, wherein said insulated gate electrode extends opposite said first and second source regions, said first and second base regions and said transition region.

13. The device of claim 4, wherein the peak first conductivity type dopant concentration in said transition region is greater than about 1×

10¹⁷ cm<sup>−

−

3</sup>;

wherein the surface defines an interface between said insulated gate electrode and said transition region; and

wherein a first conductivity type dopant concentration in said transition region is less than about 2×

10<sup>16 cm−

3</sup> at the surface.

14. The device of claim 3, wherein said first insulated electrode ohmically contacts said first base region and said first source region at the sidewall of the first trench.

15. The device of claim 9, wherein the non-rectifying junction extends between said first and second shielding regions.

16. The device of claim 1, further comprising a third trench in said semiconductor substrate, said second and third trenches defining a dummy mesa therebetween into which the drift region extends.

17. The device of claim 16, further comprising a third base region of second conductivity type that extends in the dummy mesa and is electrically connected to said first and second source regions.

18. The device of claim 17, wherein a width of the dummy mesa extending between said second and third trenches equals a width of the mesa extending between said first and second trenches.

19. The device of claim 16, further comprising:

a third insulated electrode in said third trench;

a field plate insulating layer on the dummy mesa; and

a source electrode that extends on said field plate insulating layer and is electrically connected to said first, second and third insulated electrodes.

20. The device of claim 19, wherein a spacing between said first and second trenches is unequal to the spacing between said second and third trenches.

21. A vertical power device, comprising:

a semiconductor substrate;

a drift region of first conductivity type in said semiconductor substrate;

first and second spaced-apart base regions of second conductivity type in said semiconductor substrate;

first and second source regions of first conductivity type in said first and second base regions, respectively;

a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to a surface of said semiconductor substrate; and

an insulated gate electrode that extends on the surface and opposite said first base region and said transition region.

22. The device of claim 21, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

23. The device of claim 21, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10<sup>12 cm−

2</sup>.

24. The device of claim 21, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

25. The device of claim 21, further comprising:

a first shielding region of second conductivity type that extends between said first base region and the drift region and is more highly doped than said first base region; and

a second shielding region of second conductivity type that extends between said second base region and the drift region and is more highly doped than said second base region.

26. The device of claim 25, wherein said first and second shielding regions form respective P-N rectifying junctions with said transition region;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width between said first and second shielding regions is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

27. The device of claim 26, wherein the peak first conductivity type dopant concentration in said transition region is greater than about 1×

10¹⁷ cm<sup>−

3</sup>;

wherein the surface defines an interface between said insulated gate electrode and said transition region; and

wherein a first conductivity type dopant concentration in said transition region is less than about 2×

10¹⁶ cm<sup>−

3</sup> at the surface.

29. The vertical power device of claim 28, further comprising:

a transition region of first conductivity type that extends between said first base region and a sidewall of the second trench, forms a P-N rectifying junction and a non-rectifying junction with said first base region and the drift region, respectively, and has a vertically retrograded first conductivity type doping profile relative to a surface of the mesa on which said insulated gate electrode extends.

30. The vertical power device of claim 28, further comprising:

a transition region of first conductivity type that extends between said first base region and a sidewall of the second trench, forms a P-N rectifying junction and a non-rectifying junction with said first base region and the drift region, respectively;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

28. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches, respectively;

a first base region of second conductivity type that extends opposite a sidewall of the first trench and in the mesa;

a first shielding region of second conductivity type that extends opposite the sidewall of the first trench, is more highly doped than said first base region, is disposed between said first base region and the drift region and forms a P-N rectifying junction with the drift region;

a source region of first conductivity type in said first base region;

an insulated gate electrode that extends on the mesa and opposite said first base region; and

a source electrode that extends on said source region and is electrically connected to said first and second insulated electrodes.

31. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region; and

a transition region of first conductivity type that extends between said first and second base regions and forms a non-rectifying junction with the drift region, said transition region having a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

32. The vertical power device of claim 31, wherein a product of a width of the mesa and a quantity of first conductivity type charge in a portion of the mesa extending below the transition region is preferably in a range between 2×

10⁹ cm<sup>−

1</sup> and 2×

10¹⁰ cm<sup>−

1</sup>.

33. The vertical power device of claim 31, further comprising third and fourth trenches in said semiconductor substrate, said second and third trenches defining a first dummy mesa therebetween into which the drift region extends and said third and fourth trenches defining a second dummy mesa therebetween into which the drift region extends.

35. The device of claim 34, further comprising a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to the surface;

and wherein said source electrode extends between opposing sidewalls of the first and second insulated gate electrodes.

36. The device of claim 35, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

37. The device of claim 36, wherein said conductive region comprises a dummy gate electrode.

38. The device of claim 35, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

39. The device of claim 35, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

34. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

a first insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region;

a second insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said second base region;

a conductive region that extends between said first and second insulated gate electrodes and opposite the mesa; and

a source electrode that is electrically connected to said first and second source regions and to said conductive region.

40. A method of forming a vertical power device, comprising the steps of:

implanting transition region dopants of first conductivity type at a first dose level and first energy level into a surface of a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent the surface;

forming a gate electrode that extends opposite the implanted transition region dopants, on the surface;

implanting shielding region dopants of second conductivity type at a second dose level and second energy level into the surface, using the gate electrode as an implant mask;

implanting base region dopants of second conductivity type at a third dose level and third energy level into the surface, using the gate electrode as an implant mask;

driving the implanted transition, shielding and base region dopants into the substrate to define a transition region that extends in the drift region and has a vertically retrograded first conductivity type doping profile therein relative to the surface, first and second shielding regions that extend on opposite sides of the transition region and form respective P-N rectifying junctions therewith and first and second base regions that extend on opposite sides of the transition region and form respective P-N rectifying junctions therewith; and

implanting source region dopants of first conductivity type into the first and second base regions, using the gate electrode as an implant mask.

41. The method of claim 40, wherein the first dose and energy levels and a duration of said driving step are of sufficient magnitude that a product of a peak first conductivity type dopant concentration in the transition region and a width of the transition region, as measured between the first and second shielding regions, is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

42. The method of claim 40, wherein said step of implanting shielding region dopants is preceded by the steps of:

forming trenches in the semiconductor substrate;

lining the trenches with trench insulating layers; and

then

forming conductive regions on the trench insulating layers.

43. The method of claim 42, wherein said step of implanting transition region dopants comprises implanting transition region dopants into the conductive regions within the trenches and into mesas defined between the trenches.

44. The method of claim 42, further comprising the steps of:

etching back the trench insulating layers to expose the source, base and shielding regions; and

forming a source contact that ohmically contacts the conductive, source, base and shielding regions.

45. The method of claim 40, wherein the first and second energy levels are at respective levels that cause a depth of a peak second conductivity type dopant concentration in the shielding region to be within 10% of a depth of a peak first conductivity type dopant concentration in the transition region, when the depths of the peaks are measured relative to the surface.

46. The method of claim 40, wherein the gate electrode is an insulated gate electrode;

wherein the transition region extends to an interface between the insulated gate electrode and the surface; and

wherein a peak first conductivity type dopant concentration in the transition region is greater than about ten times a surface dopant concentration in the transition region.

47. The method of claim 41, wherein said step of implanting shielding region dopants is preceded by the steps of:

forming trenches in the semiconductor substrate;

lining the trenches with trench insulating layers; and

then

forming conductive regions on the trench insulating layers.

48. The method of claim 47, further comprising the steps of:

etching back the trench insulating layers to expose the source, base and shielding regions; and

forming a source contact that ohmically contacts the conductive, source, base and shielding regions.

49. The method of claim 47, wherein the first and second energy levels are at respective levels that cause a depth of a peak second conductivity type dopant concentration in the shielding region to be within 10% of a depth of the peak first conductivity type dopant concentration in the transition region, when the depths of the peaks are measured relative to the surface.

50. The method of claim 41, wherein the gate electrode is an insulated gate electrode;

wherein the transition region extends to an interface between the insulated gate electrode and the surface; and

wherein the peak first conductivity type dopant concentration in the transition region is greater than about ten times a surface dopant concentration in the transition region.

51. A method of forming a vertical power device, comprising the steps of:

forming a trench in a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent a sidewall of the trench;

lining the trench with a trench insulating layer;

forming a trench-based electrode on the trench insulating layer;

forming an insulated gate electrode on a surface of the substrate;

forming a base region of second conductivity type that extends in the substrate and to the sidewall of the trench;

forming a source region of first conductivity type that extends in the base region and to the sidewall of the trench;

etching back the trench insulating layer to expose portions of the base and source regions that extend along the sidewall of the trench; and

forming a source contact that is electrically connected to the base and source regions along the sidewall of the trench.

52. An integrated power device having active and dummy cells therein, comprising:

a semiconductor substrate a drift region of first conductivity type therein;

first, second, third and fourth trenches spaced-apart trenches in said semiconductor substrate, said first and second trenches defining an active mesa therebetween into which the drift region extends, said second and third trenches defining a first dummy mesa therebetween into which the drift region extends and said third and fourth trenches defining a second dummy mesa therebetween into which the drift region extends;

first, second, third and fourth insulated electrodes in said first, second, third and fourth trenches, respectively;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region; and

a transition region of first conductivity type that extends between said first and second base regions and forms a non-rectifying junction with the drift region, said transition region having a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate; and

wherein the first and second dummy mesas are devoid of a forward on-state current path.

53. The device of claim 52, wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>; and

wherein a product of a width of the mesa and a quantity of first conductivity type charge in a portion of the mesa extending below the transition region is preferably in a range between 2×

10⁹ cm<sup>−

1</sup> and 2×

10¹⁰ cm<sup>−

1</sup>.