Device improvement by lowering LDD resistance with new silicide process

• US 20020175371A1
• Filed: 04/16/2001
• Published: 11/28/2002
• Est. Priority Date: 06/02/1999
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Horstmann, Manfred, Wieczorek, Karsten, Hause, Frederick N.
• Application Number:
  US10/195,566
• Publication Number:
  US 20020175371A1
• Time in Patent Office: Days
• US Class Current: 257/344
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the dielectric layer above the gate conductor and above the LDD region. The method also includes forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region and saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

Claims

1. A method for fabricating a semiconductor device on a structure, the method comprising:

forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure;

removing a first portion of the dielectric layer above the gate conductor and above the LDD region;

forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD region; and

saliciding the first conductive layer above the gate conductor and above the LDD region to form a salicided first conductive layer.

2. The method of claim 1, the method further comprising:

forming a dielectric spacer adjacent a second portion the dielectric layer adjacent the gate conductor;

introducing a dopant into a source/drain region of the structure;

forming a second conductive layer adjacent the dielectric spacer and above the salicided first conductive layer above the gate conductor and above the source/drain region; and

saliciding the second conductive layer above the gate conductor and above the source/drain region to form a salicided second conductive layer.

3. The method of claim 2, wherein forming the first conductive layer includes forming the first conductive layer from one of tungsten, molybdenum and cobalt and wherein forming the second conductive layer includes forming the second conductive layer from one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

4. The method of claim 1, wherein forming the dielectric layer includes forming the dielectric layer from one of an oxide and an oxynitride.

5. The method of claim 2, wherein forming the dielectric spacer includes forming the dielectric spacer from a material selective to the salicided first conductive layer.

6. A method for fabricating a MOSFET on a substrate, the method comprising:

forming a dielectric layer adjacent a gate conductor of the MOSFET and above LDD regions of the substrate;

removing a first portion of the dielectric layer above the gate conductor and above the LDD regions;

forming a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD regions;

saliciding the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer;

forming dielectric spacers adjacent a second portion the dielectric layer adjacent the gate conductor;

introducing a dopant into source/drain regions of the substrate;

forming a second conductive layer adjacent the dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions; and

saliciding the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer.

7. The method of claim 6, wherein forming the first conductive layer includes forming the first conductive layer from one of tungsten, molybdenum and cobalt.

8. The method of claim 6, wherein forming the second conductive layer includes forming the second conductive layer from one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

9. The method of claim 6, wherein forming the dielectric layer includes forming the dielectric layer from one of an oxide and an oxynitride.

10. The method of claim 6. wherein forming the dielectric spacers includes forming the dielectric spacers from a material selective to the salicided first conductive layer.

11. A method for fabricating a MOSFET on a substrate, the method comprising:

depositing a dielectric layer adjacent a gate conductor and gate dielectric of the MOSFET and above LDD regions of the substrate;

etching away a first portion of the dielectric layer above the gate conductor and above the LDD regions;

depositing a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD regions;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer;

forming dielectric spacers adjacent a second portion the dielectric layer adjacent the gate conductor and the gate dielectric;

implanting a dopant into source/drain regions of the substrate;

depositing a second conductive layer adjacent the dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer.

12. The method of claim 11, wherein depositing the first conductive layer includes depositing one of tungsten, molybdenum and cobalt.

13. The method of claim 11, wherein depositing the second conductive layer includes depositing one of titanium, tantalum, nickel. zirconium, tungsten, molybdenum and cobalt.

14. The method of claim 11, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

15. The method of claim 11, wherein forming the dielectric spacers includes forming the dielectric spacers from a material selective to the salicided first conductive layer.

17. The method of claim 16, wherein implanting the one of phosphorus and boron into source/drain regions of the substrate includes subjecting the source/drain regions to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds.

18. The method of claim 16, wherein depositing the first conductive layer includes depositing one of tungsten, molybdenum and cobalt and depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

19. The method of claim 16, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

20. The method of claim 16, wherein depositing the first conductive layer includes depositing cobalt and forming the dielectric spacers includes forming the dielectric spacers from an oxynitride.

16. A method for fabricating a MOSFET on a substrate, the method comprising:

depositing a dielectric layer adjacent a gate conductor and gate dielectric of the MOSFET and above LDD regions of the substrate, the dielectric layer having a thickness in a range of about 50 Å

-300 Å and

the LDD regions having been implanted with an LDD dose of one of arsenic and boron difluoride and subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds, the LDD dose ranging from about 1.0×

10¹⁴-1.0×

10¹⁵ ions/cm² at an implant energy ranging from about 3-50 keV;

etching away a First portion of the dielectric layer above the gate conductor and above the LDD regions using anisotropic reactive ion etching;

depositing a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD regions, the first conductive layer having a thickness in a range of about 50 Å

-150 Å

;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer, the first conductive layer being subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, a distance between the salicided first conductive layer and a junction between the LDD regions and the substrate being in a range of at least about 50 Å

-200 Å

;

forming dielectric spacers adjacent a second portion the dielectric layer adjacent the gate conductor and the gate dielectric, the dielectric spacers having a base thickness in a range of about 300 Å

-1500 Å

;

implanting one of phosphorus and boron into source/drain regions of the substrate, a dose of the one of phosphorus and boron ranging from about 1.0×

10¹⁵-5.0×

10¹⁵ ions/cm² at an implant energy ranging from about 30-100 keV;

depositing a second conductive layer adjacent the dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions, the second conductive layer having a thickness in a range of about 100 Å

-400 Å

; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer, the second conductive layer being subjected to an initial rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, the second conductive layer being subjected to wet chemical strip to remove unsilicided portions of the second conductive layer, the second conductive layer being subjected to a final rapid thermal anneal process performed at a temperature ranging from approximately 800-1000°

C. for a time ranging from approximately 10-60 seconds, a distance between the salicided second conductive layer and a junction between the source/drain regions and the substrate being in a range of at least about 50 Å

-200 Å

.

21. A semiconductor device comprising:

a structure;

a gate dielectric above the structure;

a gate conductor above the gate dielectric;

an LDD region of the structure adjacent the gate dielectric and the gate conductor;

a dielectric layer adjacent the gate conductor and the gate dielectric; and

a salicided first conductive layer above the gate conductor and above the LDD region.

22. The semiconductor device of claim 21, the semiconductor device further comprising:

a dielectric spacer adjacent the dielectric layer adjacent the gate conductor;

a source/drain region of the structure adjacent the dielectric spacer; and

a salicided second conductive layer above the gate conductor and above the source/drain region.

23. The semiconductor device of claim 22, wherein the first conductive layer includes one of tungsten, molybdenum and cobalt and wherein the second conductive layer includes one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

24. Thc semiconductor device of claim 21, wherein the dielectric layer includes one of an oxide and an oxynitride.

25. The semiconductor device of claim 22, wherein the dielectric spacer includes a material selective to the salicided first conductive layer.

27. The MOSFET of claim 26, wherein the first conductive layer includes one of tungsten, molybdenum and cobalt.

28. The MOSFET of claim 26. wherein the second conductive layer includes one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

29. The MOSFET of claim 26. wherein the dielectric layer includes one of an oxide and an oxynitride.

30. The MOSFET of claim 26, wherein the dielectric spacers include a material selective to the salicided first conductive layer.

26. A MOSFET comprising:

a substrate;

a gate dielectric above the substrate;

a gate conductor above the gate dielectric;

LDD regions of the substrate adjacent the gate dielectric and the gate conductor;

a dielectric layer adjacent the gate conductor and the gate dielectric;

a salicided first conductive layer above the gate conductor and above the LDD regions;

dielectric spacers adjacent the dielectric layer adjacent the gate conductor;

source/drain regions of the substrate adjacent the dielectric spacers; and

a salicided second conductive layer above the gate conductor and above the source/drain regions.

31. A MOSFET on a substrate formed by a method comprising:

depositing a dielectric layer adjacent a gate conductor and gate dielectric of the MOSFET and above LDD regions of the substrate;

etching away a first portion of the dielectric layer above the gate conductor and above the LDD regions;

depositing a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD regions;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer;

forming dielectric spacers adjacent a second portion the dielectric layer adjacent the gate conductor and the gate dielectric;

implanting a dopant into source/drain regions of the substrate;

depositing a second conductive layer adjacent the dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer.

32. The MOSFET of claim 31, wherein depositing the first conductive layer includes depositing one of tungsten, molybdenum and cobalt.

33. The MOSFET of claim 31, wherein depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

34. The MOSFET of claim 31, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

35. The MOSFET of claim 31, wherein forming the dielectric spacers includes forming the dielectric spacers from a material selective to the salicided first conductive layer.

37. The MOSFET of claim 36, wherein implanting the one of phosphorus and boron into source/drain regions of the substrate includes subjecting the source/drain regions to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds.

38. The MOSFET of claim 36, wherein depositing the first conductive layer includes depositing one of tungsten, molybdenum and cobalt and depositing the second conductive layer includes depositing one of titanium, tantalum, nickel, zirconium, tungsten, molybdenum and cobalt.

39. The MOSFET of claim 36, wherein depositing the dielectric layer includes depositing one of an oxide and an oxynitride.

40. The MOSFET of claim 36, wherein depositing the first conductive layer includes depositing cobalt and forming the dielectric spacers includes forming the dielectric spacers from an oxynitride.

36. A MOSFET on a substrate formed by a method comprising:

depositing a dielectric layer adjacent a gate conductor and gate dielectric of the MOSFET and above LDD regions of the substrate, the dielectric layer having a thickness in a range of about 50 Å

-300 Å and

the LDD regions having been implanted with an LDD dose of one of arsenic and boron difluoride and subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 800-1100°

C. for a time ranging from approximately 5-60 seconds, the LDD dose ranging from about 1.0×

10¹⁴-1.0×

10¹⁵ ions/cm² at an implant energy ranging from about 3-50 keV;

etching away a first portion of the dielectric layer above the gate conductor and above the LDD regions using anisotropic reactive ion etching;

depositing a first conductive layer above the gate conductor, adjacent the dielectric layer and above the LDD regions. the first conductive layer having a thickness in a range of about 50 Å

-150 Å

;

annealing the first conductive layer above the gate conductor and above the LDD regions to form a salicided first conductive layer, the first conductive layer being subjected to a rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, a distance between the salicided first conductive layer and a junction between the LDD regions and the substrate being in a range of at least about 50 Å

-200 Å

;

forming dielectric spacers adjacent a second portion the dielectric layer adjacent the gate conductor and the gate dielectric, the dielectric spacers having a base thickness in a range of about 300 Å

-1500 Å

;

implanting one of phosphorus and boron into source/drain regions of the substrate, a dose of the one of phosphorus and boron ranging from about 1.0×

10¹⁵-5.0×

10¹⁵ ions/cm² at an implant energy ranging from about 30-100 keV;

depositing a second conductive layer adjacent the dielectric spacers and above the salicided first conductive layer above the gate conductor and above the source/drain regions, the second conductive layer having a thickness in a range of about 100 Å

-400 Å

; and

annealing the second conductive layer above the gate conductor and above the source/drain regions to form a salicided second conductive layer, the second conductive layer being subjected to an initial rapid thermal anneal process performed at a temperature ranging from approximately 450-800°

C. for a time ranging from approximately 15-60 seconds, the second conductive layer being subjected to wet chemical strip to remove unsilicided portions of the second conductive layer, the second conductive layer being subjected to a final rapid thermal anneal process performed at a temperature ranging from approximately 800-1000°

C. for a time ranging from approximately 10-60 seconds, a distance between the salicided second conductive layer and a junction between the source/drain regions and the substrate being in a range of at least about 50 Å

-200 Å

.