Process for forming MOS-gated power device having segmented trench and extended doping zone
First Claim
1. A trench MOS-gated device comprising:
- a substrate including an upper layer, said substrate comprising doped monocrystalline semiconductor material of a first conduction type;
an extended trench in said upper layer, said trench comprising two segments having differing widths relative to one another, a bottom segment of lesser width filled with a dielectric material and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, said filled upper segment of said trench forming a gate region;
a doped extended zone of a second opposite conduction type extending from an upper surface into said upper layer on only one side of said extended trench;
a doped well region of said second conduction type overlying a drain zone of said first conduction type in said upper layer on the opposite side of said trench, said drain zone being substantially insulated from said extended zone by said bottom segment of said trench;
a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type disposed at said upper surface in said well region only on the side of said trench opposite said doped extended zone;
an interlevel dielectric layer on said upper surface overlying said gate and source regions; and
a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.
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Abstract
A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench. The drain zone is substantially insulated from the extended zone by the dielectric-filled bottom segment of the trench. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type is disposed at the upper surface of the well region only on the side of said trench opposite doped extended zone. An interlevel dielectric layer is disposed on the upper surface overlying the gate and source regions, and a metal layer disposed on the upper surface of the upper layer and the interlevel dielectric layer is in electrical contact with the source and body regions and the extended zone. A process for constructing a trench MOS-gated device comprises: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.
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Citations
30 Claims
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1. A trench MOS-gated device comprising:
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a substrate including an upper layer, said substrate comprising doped monocrystalline semiconductor material of a first conduction type;
an extended trench in said upper layer, said trench comprising two segments having differing widths relative to one another, a bottom segment of lesser width filled with a dielectric material and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, said filled upper segment of said trench forming a gate region;
a doped extended zone of a second opposite conduction type extending from an upper surface into said upper layer on only one side of said extended trench;
a doped well region of said second conduction type overlying a drain zone of said first conduction type in said upper layer on the opposite side of said trench, said drain zone being substantially insulated from said extended zone by said bottom segment of said trench;
a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type disposed at said upper surface in said well region only on the side of said trench opposite said doped extended zone;
an interlevel dielectric layer on said upper surface overlying said gate and source regions; and
a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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18. A process for forming a trench MOS-gated device, said process comprising:
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providing a substrate having an upper surface and comprising doped monocrystalline semiconductor material of a first conduction type;
forming a trench in an upper layer of said substrate, said trench having a floor and sidewalls, said trench further having a width and extending to a depth substantially corresponding to a width and a depth of the upper segment of an extended trench comprising an upper segment and a bottom segment;
forming a conformal masking oxide layer on said substrate upper layer and on said trench floor and sidewalls;
anisotropically etching said conformal masking oxide layer, thereby removing said masking oxide from said trench floor and forming an opening to substrate semiconductor material underlying said floor;
etching said semiconductor material underlying said trench floor, thereby forming said bottom segment of said extended trench, said bottom segment having a lesser width relative to a greater width of said trench upper segment and extending to a depth corresponding to the total depth of said extended trench;
removing remainder of conformal masking oxide layer from said substrate upper layer and from said trench sidewalls;
substantially filling said extended trench with a dielectric material;
selectively implanting and diffusing a dopant of a second opposite conduction type into said upper layer on one side of said extended trench, thereby forming an extended zone extending from said substrate upper surface into said upper layer;
selectively removing said dielectric material from said upper segment of said extended trench, leaving said bottom segment of said extended trench substantially filled with said dielectric material;
forming floor and sidewalls comprising dielectric material in said upper segment of said extended trench and substantially filling said upper segment with a conductive material, thereby forming a gate region in said upper segment of said extended trench;
forming a doped well region of said second conduction type in said upper layer on the side of said extended trench opposite said extended zone;
forming a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type in said well region at said upper surface;
forming an interlevel dielectric layer on said upper surface overlying said gate and source regions; and
forming a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.
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Specification