Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations

• US 20020175743A1
• Filed: 01/09/2002
• Published: 11/28/2002
• Est. Priority Date: 01/09/2001
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Granted Patent: US 6,847,248 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.

Claims

1. A method of protecting an integrated circuit from over voltage, the method comprising:

accepting a voltage from a power supply input to the integrated circuit;

accepting a pad voltage from an external voltage source;

comparing the power supply voltage to a predetermined value; and

using the pad voltage to generate a bias voltage for the integrated circuit when the power supply is below the predetermined value.

2. A method as in claim 1 wherein the generation of the bias voltage comprises:

coupling the pad voltage into a drain of a PMOS (P-channel Metal Oxide Semiconductor) device; and

coupling the power supply voltage into a gate of the PMOS device.

3. A method as in claim 2 wherein using the pad voltage to generate a bias voltage for the integrated circuit further comprises:

coupling the drain of the PMOS device to the pad voltage; and

using the source voltage of the PMOS device to couple the pad voltage to the bias voltage.

4. A method as in claim 2 wherein coupling the pad voltage into the drain of a MOS (Metal Oxide Semiconductor) device comprises:

providing the pad voltage to an input of a plurality of diode connected MOS devices; and

coupling an output of the plurality of diode connected MOS devices to the drain of the MOS device.

5. A method for generating a bias voltage (bias_mid) from a pad voltage (Vpad), when a power supply (V_DDO) is not present the method comprising:

providing V_DDO to a first semiconductor device;

providing bias-mid to the first semiconductor device such that the first semiconductor device will turn off when bias_mid−

V_DDO exceeds the threshold of the first semiconductor device; and

using the turn off of the first semiconductor device to couple Vpad to bias_mid.

6. The method of claim 5 wherein using the turn off of the first semiconductor device to couple Vpad to bias_mid further comprises:

turning on a second semiconductor device and turning off a third semiconductor device which are coupled together thereby providing a turn on voltage for a fourth semiconductor device; and

using the turn on of the fourth semiconductor device to couple Vpad to bias_mid.

7. A method for generating a voltage for biasing a device well, the method comprising:

providing a semiconductor device disposed between the device well and an input/output pad; and

turning on the semiconductor device when V_DDO is lower than the pad voltage (Vpad), thereby coupling Vpad to the device well.

8. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:

accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad;

accepting an output enable signal;

accepting a first input voltage V_DDO;

accepting a second input voltage V_DDP;

providing V_DDP voltage to Bias_Mid if the output enable signal is at an enable value; and

providing a voltage to bias_mid that is proportional to the pad voltage if the output enable signal is at a disable value.

9. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:

accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad;

accepting a power supply voltage (V_DDO);

accepting a voltage V_DDP;

providing a bias voltage to Bias_Mid, the bias voltage in a range having a maximum value of V_DDP+an offset voltage V_T and a minimum value of V_DDO−

an offset voltage V_TP, if V_DDO is greater than a predetermined value; and

providing a bias voltage to Bias_Mid that is proportional to Vpad if V_DDO is not greater than a predetermined value.

10. A method as in claim 9 wherein V_DDP is equal to V_DDO.

11. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:

accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad;

accepting a power supply voltage V_DDO;

accepting a voltage V_SSC;

providing a bias voltage to Bias_Mid, the bias voltage being in a range between V_SSC+nV_T and V_DDO−

Vat if V_DDO is greater than a predetermined value; and

providing a bias voltage to Bias_Mid, that is proportional to V_PAD if V_DDO is not greater than a predetermined value.

12. A method as in claim 11 wherein V_SSC is equal to zero volts.

14. The method of claim 13 where the predetermined value is approximately 3.3 Volts.

18. An apparatus as in claim 17 wherein VSSC is equal to ground potential.

19. An apparatus as in claim 17 wherein nV_T and V_Tp are the same.

13. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:

accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad;

accepting a power supply voltage V_DDO;

providing a voltage derived from V_DDO to Bias_Mid if V_DDC is greater than a predetermined value and providing a voltage derived from V_PAD to Bias_Mid if V_DDO is not greater than the predetermined value.

15. A method for generating a bias voltage (bias_mid) using a bias circuit the method comprising:

accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad;

accepting a power supply voltage V_DDO;

accepting a second voltage V_DDP;

providing a voltage derived from V_DDO and V_DDP to Bias_Mid if V_DDO and V_DDP are greater than predetermined values; and

providing voltage derived from V_PAD to Bias_Mid if V_DDO and V_DDP are not greater than predetermined values.

16. A method for generating a bias voltage (bias_mid) using a bias circuit tie method comprising:

accepting an input/output circuit pad voltage (Vpad) from an input/output circuit pad;

accepting a power supply voltage V_DDO;

accepting a second voltage V_DDP;

providing a voltage derived from V_DDO or V_DDP to Bias_Mid if V_DDO or V_DDP are greater than predetermined values; and

providing voltage derived from V_PAD to Bias_Mid if V_DDO and V_DDP are not greater than predetermined values.

17. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device, said fourth bias voltage in a range having a maximum value of V_SSC+nV_T, and a minimum value of V_DDO−

V_Tp, when V_DDO is greater than a predetermined value, and wherein nV_T and V_Tp are offset voltages, and when V_DDO is not greater than a predetermined value the fourth bias voltage is derived from the pad voltage;

20. An apparatus for providing an input output from an integrated circuit, the apparatus comprising:

an input/output (I/O) pad;

an upper pair of P-channel Metal Oxide Semiconductor (PMOS) devices, a first of the upper PMOS devices having source coupled to a power supply (V_DDO) and drain coupled to source of a second upper PMOS device, the second PMOS device having drain coupled to the I/O pad;

a lower pair of N-channel MOS devices (NMOS), a first of the upper NMOS devices having a drain coupled to the I/O pad and a source coupled to a drain of a second lower NMOS device, the second NMOS device having a source coupled to a ground potential;

a first bias circuit coupled to a gate of the first upper PMOS device, said bias circuit providing a first bias voltage to the gate of the first upper PMOS device when the I/O pad is in an output mode and V_DDO voltage otherwise;

a second bias circuit coupled to a gate of the second lower NMOS device, said bias circuit providing a second bias voltage to the gate of the second lower NMOS device when the I/O pad is in an output mode and a ground voltage otherwise;

a third bias circuit coupled to a gate of the second upper PMOS device, said bias circuit providing a third bias voltage to the gate of the second upper MOS device; and

a fourth bias circuit coupled to a gate of the first lower NMOS device, said bias circuit providing a fourth bias voltage to the gate of the first lower MOS device depending on the voltage on the I/O pad (V_PAD), and wherein the fourth bias voltage is in a range having a maximum value of V_DDO+V_Tp and a minimum value of V_DDO−

V_TP when V_DDO is greater than a predetermined value, where V_T and V_Tp are offset voltages.

21. An apparatus as in claim 20 wherein VSSC is at ground potential.

22. An apparatus as in claim 20 wherein V_T and V_Tp are the same offset voltages.