Active plate

• US 20020176031A1
• Filed: 05/20/2002
• Published: 11/28/2002
• Est. Priority Date: 05/23/2001
• Status: Active Grant

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Deane, Steven C.
• Granted Patent: US 6,912,037 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

The storage capacitor of an active matrix liquid crystal display is formed to have a second electrode (28) that laterally overlaps a first electrode (10). The drain (30) of a thin film transistor extends across the gate electrode (2). The gate electrode (2) and the first electrode (10) of the storage capacitor are formed from a single metallization layer. The width of the gate electrode (2) and the first electrode (10) will tend to vary in parallel, as a result of process variation. This parallel variation tends to cancel out subsequent variation in the kick back voltage.

Claims

1. An active plate, comprising:

a substrate;

a first metallisation layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate;

a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes;

a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and

an insulation layer between first and second storage capacitor electrodes,

wherein the drain electrode extends across the width of the gate electrode, and the second storage capacitor electrode overlaps the lateral edges of the first storage capacitor electrode.

2. An active plate according to claim 1 wherein the width of the gate electrode is from 0.8 to 1.2 times the width of the first storage capacitor electrode.

3. An active plate according to claim 1 wherein the semiconductor body extends longitudinally over the gate electrode.

4. An active plate according to claim 1 wherein the second storage capacitor electrode is formed from a plurality of elements having a width within a factor of 2 of the width of the drain electrode.

5. An active plate according to claim 4 wherein the plurality of elements extend laterally across the first storage capacitor electrode.

6. An active plate according to claim 5 wherein the second storage capacitor electrode is formed from a plurality of elements extending laterally across the width of the first capacitor electrode and connected together by at least one longitudinal element.

7. A liquid crystal display comprising an active plate, a passive plate and liquid crystal between the active and passive plates, the active plate comprising a substrate;

a first metallisation layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate;

a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes;

a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and

an insulation layer between first and second storage capacitor electrodes,

wherein the drain electrode extends across the width of the gate electrode, and the second storage capacitor electrode overlaps the lateral edges of the first storage capacitor electrode.

8. A method of manufacture of an active plate, comprising the steps of:

depositing and patterning using a lower definition patterning process a first metallisation layer on a substrate, the first metallisation layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate;

depositing an insulation layer;

depositing and patterning using a lower definition patterning process a semiconductor body layer forming thin film transistor bodies; and

depositing and patterning using a higher definition process a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes,

wherein the second storage capacitor electrodes overlap the lateral edges of the first storage capacitor electrode.

9. A method according to claim 8 wherein the drain electrode extends across the width of the gate electrode.

10. A method according to claim 8 wherein the higher definition process is photolithography and the lower definition process is printing.