Dram technology compatible processor/memory chips

• US 20020176313A1
• Filed: 07/09/2002
• Published: 11/28/2002
• Est. Priority Date: 02/26/1999
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Cloud, Eugene H.
• Granted Patent: US 7,023,040 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Claims

1. A method for forming a DRAM/EEPROM chip, comprising:

forming a plurality of dynamic random access memory (DRAM) access transistors on a semiconductor substrate;

forming a plurality of stacked capacitors in a subsequent level above the plurality of DRAM access transistors and separated from the plurality of DRAM access transistors by an insulator layer; and

coupling a first group of the plurality of stacked capacitors to a gate for each DRAM access transistor in a first group of the plurality of DRAM access transistors;

coupling a second group of the plurality of stacked capacitors to a diffused region in a second group of the plurality of DRAM access transistors.

2. The method of claim 1, wherein forming a plurality of DRAM access transistors includes forming a plurality of n-channel metal oxide semiconductor (NMOS) transistors.

3. The method of claim 1, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors having a bottom plate, a capacitor dielectric, and a top plate, wherein the bottom plate is formed in a cup shape having interior walls, the capacitor dielectric is formed conformal to the bottom plate and the top plate is formed conformal to the capacitor dielectric, and wherein forming the plurality of stacked capacitors includes forming a portion of the top plate within the interior walls of the bottom plate.

4. The method of claim 3, wherein coupling a first group of the plurality of stacked capacitors to a gate in each DRAM access transistors in a first group of the plurality of DRAM access transistors includes coupling the bottom plate of each stacked capacitor in the first group of the plurality of stacked capacitors to the gate for the first group of the plurality of DRAM access transistors.

5. The method of claim 1, wherein the forming a plurality of stacked capacitors includes forming the plurality of stacked capacitors according to a dynamic random access memory (DRAM) process flow.

6. A programmable logic array, comprising:

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs;

a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET);

a stacked capacitor formed according to a dynamic random access memory (DRAM) process; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

7. The programmable logic array of claim 6, wherein the first logic plane and the second logic plane each comprise NOR planes.

8. The programmable logic array of claim 6, wherein the substrate is a bulk semiconductor.

9. The programmable logic array of claim 6, wherein the electrical contact includes a polysilicon plug.

10. The programmable logic array of claim 6, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.

11. The programmable logic array of claim 6, wherein the programmable logic array is operatively coupled to a computer system.

12. The programmable logic array of claim 6, wherein the stacked capacitor includes a fin type capacitor.

13. The programmable logic array of claim 6, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the MOSFET.

15. The address decoder of claim 14, wherein the number of address lines includes a number of complementary address lines that are disposed in the array.

16. The address decoder of claim 14, wherein the decoder is operatively coupled to a dynamic random access memory (DRAM) device.

17. The address decoder of claim 14, wherein the array includes N address lines and 2^N output lines.

18. The address decoder of claim 14, wherein the number of address lines includes a number of complementary address lines that are each coupled to one of the address lines through an inverter and are disposed in the array.

20. The electronic system of claim 19, wherein the programmable logic array includes a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

21. The electronic system of claim 20, wherein the first logic plane and the second logic plane each comprise NOR planes.

22. The electronic system of claim 19, wherein:

the processor includes at least one register formed from dynamic random access memory cells; and

wherein the processor includes at least one function and sequence circuit.

23. The electronic system of claim 19, wherein the processor includes a program circuit that stores a program.

24. The electronic system of claim 23, wherein the program circuit stores the program in an EEPROM.

26. The integrated circuit of claim 25, wherein the plurality of stacked capacitors includes a plurality of stacked capacitors formed according to a dynamic random access memory (DRAM) process flow.

29. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a EEPROM.

30. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form at least one programmable logic array.

31. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a memory decode array.

32. The method of claim 28, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form at least one programmable logic array of a processor circuit.

33. The integrated circuit of claim 26, wherein the transistors includes transistors formed according to a dynamic random access memory (DRAM) process.

34. The integrated circuit of claim 33, wherein the transistors includes n-channel metal oxide semiconductor (NMOS) transistors.

35. The integrated circuit of claim 25, wherein the first sub-circuit is adapted to implement at least one of an AND logic function and a NAND logic function.

36. The integrated circuit of claim 35, wherein the second sub-circuit is adapted to implement at least one of an OR logic function and a NOR logic function.

37. The integrated circuit of claim 25, wherein the second sub-circuit is adapted to implement at least one of an AND logic function and a NAND logic function.

38. The integrated circuit of claim 37, wherein the first sub-circuit is adapted to implement at least one of an OR logic function and a NOR logic function.

40. The integrated circuit of claim 39, wherein the plurality of stacked capacitors includes a plurality of stacked capacitors formed according to a dynamic random access memory (DRAM) process flow.

41. The integrated circuit of claim 39, wherein the plurality of stacked capacitors includes a fin type capacitor.

42. The integrated circuit of claim 39, wherein one of the plurality of stacked capacitors includes a storage node, a capacitor dielectric, a plate conductor, and an electrical contact coupling the storage node to a gate of one of the plurality of metal oxide semiconductor field effect transistors.

43. The integrated circuit of claim 42, wherein the storage node is a bottom capacitor plate.

44. The integrated circuit of claim 42, wherein the storage node is adapted to act as a floating gate.

45. The integrated circuit of claim 39, the plurality of stacked capacitors includes a cup-shaped capacitor.

47. The integrated circuit of claim 46, wherein the plurality of stacked capacitors includes a plurality of stacked capacitors formed according to a dynamic random access memory (DRAM) process flow.

48. The integrated circuit of claim 46, wherein the plurality of stacked capacitors includes a fin type capacitor.

49. The integrated circuit of claim 46, wherein one of the plurality of stacked capacitors includes a storage node, a capacitor dielectric, a plate conductor, and an electrical contact coupling the storage node to the gate of one of the plurality of metal oxide semiconductor field effect transistors.

50. The integrated circuit of claim 49, wherein the storage node is the bottom plate of the capacitor and is adapted to act as a floating gate for a non-volatile memory cell.

51. The integrated circuit of claim 50, wherein the plate conductor is a top plate of the capacitor and is adapted to act as a control gate for a non-volatile memory cell.

14. An address decoder for a memory device, the address decoder comprising:

a number of address lines;

a number of output lines;

wherein the address lines, and the output lines form an array;

a number of non-volatile memory cells that are disposed at intersections of output lines and address lines, wherein each non-volatile memory cell includes a metal oxide semiconductor field effect transistor (MOSFET), a stacked capacitor formed according to a dynamic random access memory (DRAM) process, and an electrical contact that couples the stacked capacitor to a gate of the MOSFET; and

wherein the non-volatile memory cells are selectively programmed such that the non-volatile memory cells implement a logic function that selects an output line responsive to an address provided to the address lines.

19. An electronic system, comprising:

a memory; and

a processor coupled to the memory and formed on a die common with the memory; and

wherein the processor includes at least one programmable logic array including;

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET);

a stacked capacitor formed according to a dynamic random

access memory (DRAM) process; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

25. An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer;

a plurality of stacked capacitors disposed above the plurality of MOSFETs and separated from the plurality of MOSFETs by an insulator layer; and

wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;

wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit; and

wherein the first sub-circuit is operatively coupled to the second sub-circuit.

27. An integrated circuit, comprising:

a processor;

a memory, operatively coupled to the processor; and

wherein the processor and the memory are formed on the same semiconductor substrate and the processor includes at least one programmable logic array with a non-volatile memory cell that includes a metal oxide semiconductor field effect transistor with a stacked capacitor coupled to its gate.

28. A method for forming an integrated circuit, the method comprising:

forming a plurality of metal oxide semiconductor transistors (MOSFETs) in and on a layer of semiconductor material;

forming a first set of stacked capacitors that are coupled to diffusion regions of selected ones of the plurality of MOSFETs to form a memory array; and

forming, on the same layer of semiconductor material, a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a plurality of non-volatile memory cells; and

interconnecting the memory array and the non-volatile memory cells to provide the integrated circuit.

39. An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer;

a plurality of stacked capacitors disposed above the plurality of MOSFETs, each of the stacked capacitors providing a coupling ratio greater than 1.0;

an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;

wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;

wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit; and

wherein the first sub-circuit is operatively coupled to the second sub-circuit.

46. An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer, each of the MOSFETs including a channel region, a gate oxide on the channel region, and a gate on the gate oxide, wherein the gate oxide is a tunneling oxide;

a plurality of stacked capacitors disposed above the plurality of MOSFETs, each of the stacked capacitors providing a coupling ratio greater than 1.0;

an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;

wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;

wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit; and

wherein the first sub-circuit is operatively coupled to the second sub-circuit.

52. An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer, each of the MOSFETs including a channel region, a gate oxide on the channel region, and a gate on the gate oxide, wherein the gate oxide has a thickness of less than 100 Angstroms;

a plurality of stacked capacitors disposed above the plurality of MOSFETs, each of the stacked capacitors providing a coupling ratio greater than 1.0;

an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;

wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;

wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit; and

wherein the first sub-circuit is operatively coupled to the second sub-circuit.

53. The integrated circuit of claim 52, wherein the gate oxide is adapted to act as a tunneling oxide.

54. The integrated circuit of claim 53, wherein the plurality of stacked capacitors includes a plurality of stacked capacitors formed according to a dynamic random access memory (DRAM) process flow.

55. The integrated circuit of claim 52, wherein the plurality of stacked capacitors includes a fin type capacitor.

56. The integrated circuit of claim 52, wherein one of the plurality of stacked capacitors includes a storage node, a capacitor dielectric, a plate conductor, and an electrical contact coupling the storage node to the gate of one of the plurality of metal oxide semiconductor field effect transistors.

57. The integrated circuit of claim 56, wherein the storage node is the bottom plate of the capacitor and is adapted to act as a floating gate for a non-volatile memory cell.

58. The integrated circuit of claim 57, wherein the plate conductor is a top plate of the capacitor and is adapted to act as a control gate for a non-volatile memory cell.

59. An integrated circuit formed in and on a semiconductor layer, the integrated circuit comprising:

a plurality of metal oxide semiconductor field effect transistors (MOSFETs) formed in and on the semiconductor layer, each of the MOSFETs including a channel region, a gate oxide on the channel region, and a gate on the gate oxide, wherein the gate oxide is adapted to act as a tunneling oxide and has a thickness of less than 100 Angstroms;

a plurality of stacked capacitors disposed above the plurality of MOSFETs;

an insulator layer separating the plurality of stacked capacitors from the plurality of MOSFETs;

wherein a first group of the plurality of stacked capacitors is selectively coupled to gates of the MOSFETs to form non-volatile memory cells for a first sub-circuit;

wherein a second group of the plurality of stacked capacitors is selectively coupled to diffused regions of the MOSFETs to form a second sub-circuit; and

wherein the first sub-circuit is operatively coupled to the second sub-circuit.