Ultra-modular processor in lattice topology
First Claim
1. A modular operating topology element (MOTE) within a miniaturized package, comprising:
- a central processing unit (CPU);
an internal hardware bus connected to said central processing unit;
a non-volatile RAM connected to said hardware bus and accessible by said CPU;
a non-volatile ROM connected to said hardware bus and accessible by said CPU;
a battery-backed real time clock-calendar unit connected to said hardware bus for providing time and date information to said CPU;
an interrupt control module connected to said hardware bus and operating as an interrupt monitor for prompting various operating states of said CPU; and
a host bus I/O module for connecting said internal hardware bus to a prevailing standard host external bus;
wherein the RAM space is managed by said CPU as workspace memory and as a virtual passive mass storage as seen by the host external bus under interrupt-driven multiprogramming within the MOTE.
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Abstract
A Modular Operating Topology Element (MOTE) is provided within a software-latticed networked topology for implementing ultra-concurrent operation of a plurality of such elements. Each MOTE is a single miniaturized package having a prevailing standard form, e.g., Compact Flash, with an embedded a full function processor (CPU), a unique resident operating system, and dedicated applications. The external interface of each MOTE projects a virtual mass storage volume. A MOTE selectively acts as an ultra-modular processor, operating with ultra-concurrency, with the CPU internally bus connected to non-volatile RAM, dedicated non-volatile ROM (firmware), a dedicated battery-backed real-time clock-calendar unit, and a dedicated interrupt monitor unit. Internally accessed data and internal applications stored in ROM or in non-volatile RAM are invisible to the outside. Optional input/output devices may be connected to the internal hardware bus. A host external bus connection is provided which is compatible with prevailing bus standards for mass storage volumes, e.g., compact flash memory, which support file-level in prevailing format data transfers. A software-latticed network of one or more MOTEs defines a network element for a larger system. Multiple MOTEs, which define the latticed network element, are software-lattice-interconnected to operate concurrently in a non-hierarchical (ladder) interconnection using a circulating message exchange protocol compatible with physically concurrent operation of the modular processors (MOTE'"'"'s). MOTE resident software MOTE mirrors the topology of the inter-modular processor architecture, permitting support of concurrent logical processes wherein there is an exchange of messages circulated on a logical (software) bus. Each MOTE within a lattice network is dedicated to a specific function on behalf of the whole system and operates highly independently and concurrently.
40 Citations
24 Claims
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1. A modular operating topology element (MOTE) within a miniaturized package, comprising:
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a central processing unit (CPU);
an internal hardware bus connected to said central processing unit;
a non-volatile RAM connected to said hardware bus and accessible by said CPU;
a non-volatile ROM connected to said hardware bus and accessible by said CPU;
a battery-backed real time clock-calendar unit connected to said hardware bus for providing time and date information to said CPU;
an interrupt control module connected to said hardware bus and operating as an interrupt monitor for prompting various operating states of said CPU; and
a host bus I/O module for connecting said internal hardware bus to a prevailing standard host external bus;
wherein the RAM space is managed by said CPU as workspace memory and as a virtual passive mass storage as seen by the host external bus under interrupt-driven multiprogramming within the MOTE. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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15. A connection network forming a software lattice topology for the operation of identical computing elements in connection with host equipment, comprising:
- a plurality of Modular Operating Topology Elements (MOTEs) each containing a central processing unit and internal hardware bus, a non-volatile RAM connected to said internal hardware bus and accessible under the exclusive control of said CPU, a non-volatile ROM connected to said internal hardware bus and accessible exclusively by said CPU, a battery-backed real time clock-calendar unit connected to said internal hardware bus and providing time and date information to said CPU, an interrupt control module connected to said internal hardware bus and providing status signals to said CPU, and one or more optional peripheral I/O interfaces providing access to said internal hardware bus, wherein said interrupt control module operates with said CPU to independently control the ultra-concurrent and ultra-modular logical processing of operations within each said topology element, and wherein said CPU controls the access to said RAM to project virtual passive mass storage to said I/O connection;
wherein a plurality of said topology elements are each programmed with a specific logical queue address for receiving logical messages and to perform a specific system support or end-user application function.
- a plurality of Modular Operating Topology Elements (MOTEs) each containing a central processing unit and internal hardware bus, a non-volatile RAM connected to said internal hardware bus and accessible under the exclusive control of said CPU, a non-volatile ROM connected to said internal hardware bus and accessible exclusively by said CPU, a battery-backed real time clock-calendar unit connected to said internal hardware bus and providing time and date information to said CPU, an interrupt control module connected to said internal hardware bus and providing status signals to said CPU, and one or more optional peripheral I/O interfaces providing access to said internal hardware bus, wherein said interrupt control module operates with said CPU to independently control the ultra-concurrent and ultra-modular logical processing of operations within each said topology element, and wherein said CPU controls the access to said RAM to project virtual passive mass storage to said I/O connection;
Specification