Method for improving timing behavior in a hardware logic emulation system

• US 20020178427A1
• Filed: 05/25/2001
• Published: 11/28/2002
• Est. Priority Date: 05/25/2001
• Status: Abandoned Application

• Current Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Ding, Cheng-Liang, Freeman, Thomas H., Ben-Tzur, Tzvi, Chao, Liang-Fang
• Application Number:
  US09/865,873
• Publication Number:
  US 20020178427A1
• Time in Patent Office: Days
• US Class Current: 716/12
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and apparatus for shortening the time to emulation and user-friendliness of a hardware emulation system is disclosed that places adjustable delay elements at the inputs to each flip-flop in a design after the user'"'"'s design has been compiled. The user selects the amount of delay to be programmed into the adjustable delay element.

Claims

1. A method of compiling a netlist description of a logic design for programming into a hardware logic emulation system, the netlist description comprising combinational logic gates, sequential logic gates, data paths and clock paths, the sequential logic gates comprising flip-flops and latches, each of the flip-flops comprising a data input, a clock inputs and an output, the method comprising:

compiling the netlist description to create an emulation netlist, said compiling step comprising;

identifying every flip-flop in the emulation netlist;

changing the emulation netlist such that an adjustable delay element is disposed at the data input of each of the flip-flops of the netlist description; and

after said compiling step, setting a delay for said adjustable delay element to a value that eliminates the possibility of a hold time violation.

2. The method of claim 1 wherein said adjustable delay comprises a first flip-flop and a second flip flop, wherein said first flip-flop has an input, an output and a clock input, said second flip-flop has an input, an output and a clock input, said output of said first flip-flop in communication with said input of said second flip-flop.

3. The method of claim 2 wherein said delay is established in said adjustable delay element by varying frequencies input to said clock input on said first flip-flop and to said clock input on said second flip-flop.

4. A method processing a netlist description of a logic design for programming into an emulation system that eliminates hold time violations, the netlist description comprising combinational logic gates, sequential logic gates, data paths and clock paths, the sequential logic gates comprising flip-flops and latches, each of the flip-flops comprising a data input, a clock inputs and an output, the emulation system comprised of programmable logic chips interconnected together, the method comprising:

compiling the netlist description to create an emulation netlist, said compiling step comprising inserting an adjustable delay element at the data input of each of the flip-flops of the netlist description;

calculating data path delay time and clock path delay time, the clock paths and data paths may be passing through multiple of the programmable logic chips;

calculating clock skew value between a pair of flip-flops; and

setting a delay value for said adjustable delay element that makes said data path delay greater than said clock skew.

5. The method of claim 4 wherein said adjustable delay comprises a first flip-flop and a second flip flop, wherein said first flip-flop has an input, an output and a clock input, said second flip-flop has an input, an output and a clock input, said output of said first flip-flop in communication with said input of said second flip-flop.

6. The method of claim 5 wherein said delay is established in said adjustable delay element by varying frequencies input to said clock input on said first flip-flop and to said clock input on said second flip-flop.

7. The method of claim 4 further comprising removing selected ones of said adjustable delay elements from the netlist description where said data path delay already greater than said clock skew without setting said delay value.