Wiring board design aiding apparatus, design aiding method, storage medium, and computer program

• US 20020178429A1
• Filed: 05/20/2002
• Published: 11/28/2002
• Est. Priority Date: 05/22/2001
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ikeda, Hiroshi, Nakayama, Takeshi, Tanimoto, Shinichi
• Granted Patent: US 7,257,792 B2
• Time in Patent Office: Days
• US Class Current: 716/15
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H05K 1/0269 for visual or optical inspection
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/303 Surface mounted components, e.g. affixing before soldering, aligning means, spacing means H05K3/32 takes precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

In a design aiding apparatus of the present invention, a plane clearance setting unit acquires information showing a predetermined margin, a component placement unit determines a placement area of a component such that, as seen in a lamination direction of a multilayer wiring board, at least one of the component and a pad connected to the component is included within a candidate area of a plane foil excluding a perimeter area, and a wiring unit determines a placement area of a wiring foil and a via in the same way that the placement area of the component is determined. Furthermore, in regard to a component, a component pad, a wiring foil, and a via whose placement areas have already been determined, a component placement inspection unit reports a design condition violation if the placement area of at least one of the component and the pad deviates outside the candidate area as seen in the lamination direction of the board, and a wiring inspection unit reports a design condition violation if the placement area of the wiring foil or the via deviates outside the candidate area as seen in the lamination direction of the board.

Claims

1. A design aiding apparatus for aiding in a layout design of an element on a multilayer wiring board, wherein

the apparatus determines, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within an area of the plane foil excluding a perimeter area.

2. The apparatus of claim 1, wherein

a component and a pad, whose placement area is determined relative to a placement area of the component, are included as elements, and

the apparatus comprises:

plane foil placement information storage means for storing plane foil placement information showing a placement area of a plane foil whose placement area has been determined;

plane clearance information acquisition means for acquiring plane clearance information showing one or more margins; and

component placement information generation means for determining the placement area of the component such that at least one of the component and the pad, as seen in the lamination direction of the board, is included within a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information, and for generating component placement information showing the determined placement area of the component.

3. The apparatus of claim 2, further comprising:

signal attribute information acquisition means for acquiring signal attribute information showing an abruptness of a change over time of a signal transmitted from or received by the component, wherein

the component placement information generation means includes an abruptness judgment unit for judging, based on the signal attribute information, whether the abruptness of the change over time of the signal satisfies a predetermined condition, and generates component placement information only when the abruptness judgment unit judges in the affirmative.

4. The apparatus of claim 3, wherein

the signal attribute information shows at least one of a frequency, a rise time, and a fall time of the signal, and

the abruptness judgment unit judges in the affirmative if the frequency of the signal is greater than or equal to a first threshold, or if at least one of the rise time and the fall time of the signal is less than or equal to a second threshold and a third threshold, respectively.

5. The apparatus of claim 2, wherein

an inclusive area has been determined that includes the component and all pads whose placement area is determined relative to the placement area of the component, and

the component placement information generation means determines the placement area of the component such that the inclusive area, as seen in the lamination direction of the board, is included within a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information, and generates component placement information showing the determined placement area of the component.

6. The apparatus of claim 2, wherein

the component placement information generation means determines, when plane foil placement information is not stored in the plane foil placement information storage means, the placement area of the component such that at least one of the component and the pad, as seen in the lamination direction of the board, is included within an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin, and generates component placement information showing the determined placement area of the component.

7. The apparatus of claim 1, wherein

a wiring foil and a via are included as elements, and

the apparatus comprises:

plane foil placement information storage means for storing plane foil placement information showing a placement area of a plane foil whose placement area has been determined;

plane clearance information acquisition means for acquiring plane clearance information showing one or more margins;

wiring foil placement information generation means for determining a placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information, and for generating wiring foil placement information showing the determined placement area of the wiring foil; and

via placement information generation means for determining a placement area of the via such that the via, as seen in the lamination direction of the board, is included within a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information, and for generating via placement information showing the determined placement area of the via.

8. The apparatus of claim 7, further comprising:

first signal attribute information acquisition means for acquiring first signal attribute information showing an abruptness of a change over time of a first signal transmitted by the wiring foil; and

second signal attribute information acquisition means for acquiring second signal attribute information showing an abruptness of a change over time of a second signal transmitted by the via, wherein

the wiring foil placement information generation means includes a first abruptness judgment unit for judging, based on the first signal attribute information, whether the abruptness of the change over time of the first signal satisfies a predetermined condition, and generates component placement information only if the first abruptness judgment unit judges in the affirmative, and

the via placement information generation means includes a second abruptness judgment unit for judging, based on the second signal attribute information, whether the abruptness of the change over time of the second signal satisfies a predetermined condition, and generates component placement information only if the second abruptness judgment unit judges in the affirmative.

9. The apparatus of claim 8, wherein

the signal attribute information shows at least one of a frequency, a rise time, and a fall time of the first signal,

the first abruptness judgment unit judges in the affirmative if the frequency of the first signal is greater than or equal to a first threshold, or if at least one of the rise time and the fall time of the first signal is less than or equal to a second threshold and a third threshold, respectively,

the signal attribute information shows at least one of a frequency, a rise time, and a fall time of the second signal, and

the second abruptness judgment unit judges in the affirmative if the frequency of the second signal is greater than or equal to the first threshold, or if at least one of the rise time and the fall time of the second signal is less than or equal to the second threshold and the third threshold, respectively.

10. The apparatus of claim 7, wherein

the wiring foil placement information generation means further includes a wiring possibility judgment unit for judging whether it is possible to determine the placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within the first candidate area,

the wiring foil placement information generation means determines, when the wiring possibility judgment unit judges in the affirmative, the placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within the first candidate area, and generates wiring foil placement information showing the determined placement area of the wiring foil, and

the wiring foil placement information generation means determines, when the wiring possibility judgment unit judges in the negative, the placement area of the wiring foil such that, as seen in the lamination direction of the board, an overlap between the placement area of the wiring foil and the perimeter area of the plane foil having the first margin is small enough to satisfy a predetermined condition, and generates wiring foil placement information showing the determined placement area of the wiring foil.

11. The apparatus of claim 7, wherein

the wiring foil placement information generation means determines, when plane foil placement information is not stored in the plane foil placement information storage means, the placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin, and generates wiring foil placement information showing the determined placement area of the wiring foil, and

the via placement information generation means determines, when plane foil placement information is not stored in the plane foil placement information storage means, the placement area of the via such that the via, as seen in the lamination direction of the board, is included within the alternative candidate area, and generates via placement information showing the determined placement area of the via.

12. The apparatus of claim 7, wherein

a component and a pad, whose placement area is determined relative to a placement area of the component, are further included as elements, and

the apparatus further comprises:

component placement information generation means for determining the placement area of the component such that at least one of the component and the pad, as seen in the lamination direction of the board, is included within a third candidate area of the plane foil excluding a perimeter area having a third margin shown in the plane clearance information, and for generating component placement information showing the determined placement area of the component.

14. The apparatus of claim 13, wherein

a component, whose placement area has been determined, and a pad, whose placement area is determined relative to the placement area of the component, are included as elements, and

the apparatus comprises:

component placement information storage means f or storing component placement information showing the placement area of the component;

plane clearance information acquisition means for acquiring plane clearance information showing one or more margins;

component deviation judgment means for judging, when the component has been placed in accordance with the component placement information, whether the placement area of at least one of the component and the pad, as seen in the lamination direction of the board, deviates outside a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information; and

design condition violation information generation means for generating, when the component deviation judgment means judges in the affirmative, component design condition violation information showing the component.

15. The apparatus of claim 14, further comprising:

signal attribute information acquisition means for acquiring signal attribute information showing an abruptness of a change over time of a signal transmitted from or received by the component, wherein

the design condition violation information generation means includes an abruptness judgment unit for judging, based on the signal attribute information, whether the abruptness of the change over time of the signal satisfies a predetermined condition, and suppresses the generation of the component design condition violation information when the abruptness judgment unit judges in the negative.

16. The apparatus of claim 14, wherein

an inclusive area has been determined that includes the component and all pads whose placement area is determined relative to the placement area of the component, and

the component deviation judgment means judges, when the component has been placed in accordance with the component placement information, whether the inclusive area, as seen in the lamination direction of the board, deviates outside a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information.

17. The apparatus of claim 14, wherein

the component deviation judgment means judges, when plane foil placement information is not stored in the plane foil placement information storage means, whether the placement area of at least one of the component and the pad, as seen in the lamination direction of the board, deviates outside an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin.

18. The apparatus of claim 13, wherein

a wiring foil and a via, whose placement areas have been determined, are included as elements, and

the apparatus comprises:

wiring foil placement information storage means for storing wiring foil placement information showing a placement area of the wiring foil;

via placement information storage means for storing via placement information showing a placement area of the via;

plane foil placement information storage means for storing plane foil placement information showing a placement area of a plane foil whose placement area has been determined;

plane clearance information acquisition means for acquiring plane clearance information showing one or more margins;

wiring foil deviation judgment means for judging, when the wiring foil has been placed in accordance with the wiring foil placement information, whether the placement area of the wiring foil, as seen in the lamination direction of the board, deviates outside a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information;

via deviation judgment means for judging, when the via has been placed in accordance with the via placement information, whether the placement area of the via, as seen in the lamination direction of the board, deviates outside a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information; and

design condition violation information generation means for generating, when the wiring foil deviation judgment means judges in the affirmative, wiring foil design condition violation information showing the wiring foil, and for generating, when the via deviation judgment means judges in the affirmative, via design condition violation information showing the via.

19. The apparatus of claim 18, further comprising:

first signal attribute information acquisition means for acquiring first signal attribute information showing an abruptness of a change over time of a first signal transmitted by the wiring foil; and

second signal attribute information acquisition means for acquiring second signal attribute information showing an abruptness of a change over time of a second signal transmitted by the via, wherein

the design condition violation information generation means includes

a first abruptness judgment unit for judging, based on the first signal attribute information, whether the abruptness of the change over time of the first signal satisfies a predetermined condition; and

a second abruptness judgment unit for judging, based on the second signal attribute information, whether the abruptness of the change over time of the second signal satisfies a predetermined condition, and

the design condition violation information generation means suppresses the generation of the wiring foil design condition violation information when the first abruptness judgment unit judges in the negative, and suppresses the generation of the via design condition violation information when the second abruptness judgment unit judges in the negative.

20. The apparatus of claim 18, wherein

the design condition violation information generation means suppresses the generation of the wiring foil design condition violation information when the wiring foil deviation judgment means judges in the affirmative, and when the placement area of the wiring foil is such that, as seen in the lamination direction of the board, an overlap between the placement area of the wiring foil and the perimeter area of the plane foil having the first margin is small enough to satisfy a predetermined condition.

21. The apparatus of claim 18, wherein

the wiring foil deviation judgment means judges, when plane foil placement information is not stored in the plane foil placement information storage means, whether the placement area of the wiring foil, as seen in the lamination direction of the board, deviates outside an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin, and

the via deviation judgment means judges, when plane foil placement information is not stored in the plane foil placement information storage means, whether the placement area of the via, as seen in the lamination direction of the board, deviates outside an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin.

22. The apparatus of claim 18, wherein

a component, whose placement area has been determined, and a pad, whose placement area is determined relative to the placement area of the component, are further included as elements,

the apparatus further comprises:

component placement information storage means for storing component placement information showing the placement area of the component; and

component deviation judgment means for judging, when the component has been placed in accordance with the component placement information, whether the placement area of at least one of the component and the pad, as seen in the lamination direction of the board, deviates outside a third candidate area of the plane foil excluding a perimeter area having a third margin shown in the plane clearance information, and

the design condition violation information generation means generates, when the component deviation judgment means judges in the affirmative, component design condition violation information showing the component.

13. A design aiding apparatus for aiding in a layout design of an element on a multilayer wiring board, wherein the apparatus reports, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside an area of the plane foil excluding a perimeter area.

23. A design aiding method for aiding in a layout design of an element on a multilayer wiring board, comprising:

a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and

a placement information generation step of determining, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information, and of generating placement information showing the determined placement area of the element.

24. A design aiding method for aiding in a layout design of an element on a multilayer wiring board, comprising:

a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and

a design condition violation information reporting step of reporting, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information.

25. A computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, including:

a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and

a placement information generation step of determining, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information, and of generating placement information showing the determined placement area of the element.

26. A computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, including:

a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and

a design condition violation information reporting step of reporting, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information.

27. A computer-readable storage medium storing a computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, the computer program including:

a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and

a placement information generation step of determining, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information, and of generating placement information showing the determined placement area of the element.

28. A computer-readable storage medium storing a computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, the computer program including:

a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and

a design condition violation information reporting step of reporting, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information.